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Through silicon via keep out zone formation method and system

  • US 9,054,166 B2
  • Filed: 10/18/2013
  • Issued: 06/09/2015
  • Est. Priority Date: 08/31/2011
  • Status: Active Grant
First Claim
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1. A method of forming an integrated circuit (IC), the method comprising:

  • receiving a substrate having a plurality of active devices thereon; and

    forming a first through silicon via (TSV) such that none of the plurality of active devices are positioned in a first keep out zone (KOZ), the first KOZ being a region in which a stress impact of the first TSV exceeds a first threshold, the first KOZ having a first radius to a center of the first TSV in a first crystal orientation and a second radius to the center of the first TSV in a second crystal orientation, the first radius being smaller than the second radius.

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