Through silicon via keep out zone formation method and system

• US 9,054,166 B2
• Filed: 10/18/2013
• Issued: 06/09/2015
• Est. Priority Date: 08/31/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsieh, Cheng-Chieh, Teng, Hung-An, Hou, Shang-Yun, Jeng, Shin-Puu
• Primary Examiner(s): Monbleau, Davienne
• Assistant Examiner(s): WHITE, SHAKA SHAKAR
• Application Number:
  US14/057,951
• Publication Number:
  US 20140045332A1
• Time in Patent Office: 599 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.

Claims

1. A method of forming an integrated circuit (IC), the method comprising:

receiving a substrate having a plurality of active devices thereon; and

forming a first through silicon via (TSV) such that none of the plurality of active devices are positioned in a first keep out zone (KOZ), the first KOZ being a region in which a stress impact of the first TSV exceeds a first threshold, the first KOZ having a first radius to a center of the first TSV in a first crystal orientation and a second radius to the center of the first TSV in a second crystal orientation, the first radius being smaller than the second radius.

2. The method of claim 1, further comprising determining the first threshold as a percentage of drain current shift caused by the first TSV.

3. The method of claim 2, wherein the percentage is from about 10% to about 20%.

4. The method of claim 1, further comprising determining the first threshold is a mobility change percentage caused by the first TSV.

5. The method of claim 1, wherein the first KOZ has a smallest radius in a crystal orientation [010] among all orientations.

6. The method of claim 1, further comprising forming a second TSV outside of the first KOZ along a crystal orientation at which the first KOZ has a least radius to the center of the first TSV, the second TSV having a second KOZ, the second KOZ being a region in which a stress impact of the second TSV exceeds a second threshold, wherein the second KOZ and the first KOZ are disjoint.

7. The method of claim 1, wherein none of the plurality of active devices are positioned in a second KOZ, the second KOZ being a region in which the stress impact of the first TSV exceeds a second threshold.

8. The method of claim 7, further comprising determining the second threshold as a critical dimension of the first TSV, or a pitch of first the TSV to another adjacent TSV.

9. The method of claim 1, wherein the first KOZ is from about 10 μ

m to about 20 μ

m.

10. A method of forming an integrated circuit (IC), the method comprising:

forming a plurality of through silicon vias (TSVs), the plurality of TSVs having an overall keep out zone (KOZ) defined as a region in which a stress impact of one or more of the plurality of TSVs exceed a first threshold, the stress impact of each TSV varying with a crystal orientation; and

forming a plurality of active devices, none of the plurality of active devices being formed within the overall KOZ.

11. The method of claim 10, further comprising determining the first threshold as a percentage of drain current shift caused by the plurality of TSVs.

12. The method of claim 11, wherein the percentage is from about 10% to about 20%.

13. The method of claim 10, further comprising determining the first threshold is a mobility change percentage caused by the plurality of TSVs.

14. The method of claim 10, wherein the stress impact of each TSV has a smallest radius in a crystal orientation [010] among all orientations.

15. A method of forming an integrated circuit (IC), the method comprising:

forming a plurality of active devices;

forming a plurality of through silicon vias (TSVs), the plurality of TSVs being arranged in a pattern having linear segments, wherein each TSV has a respective keep out zone (KOZ), a union of the respective KOZs defining an overall KOZ for the plurality of TSVs; and

forming a plurality of TSV stress plugs at an end region of the overall KOZ of the plurality of TSVs, the stress plugs being omitted from side regions of the overall KOZ, wherein none of the plurality of active devices are located within the overall KOZ.

16. The method of claim 15, wherein a respective KOZ size of a first TSV may be determined by a first method and a respective KOZ size of a second TSV may be determined by a second method.

17. The method of claim 15, wherein the plurality of TSV stress plugs may be formed in a same process as forming the plurality of TSVs.

18. The method of claim 15, wherein the plurality of TSVs form a linear array and the plurality of TSV stress plugs are formed at ends of the linear array.

20. The method of claim 15, where the plurality of TSVs form a T-shape having three end points and the plurality of TSV stress plugs are formed at the three end points.

19. A method of forming an integrated circuit (IC), the method comprising:

forming a plurality of active devices;

forming a plurality of through silicon vias (TSVs), the plurality of TSVs being arranged in a pattern having a regular shape, wherein each TSV has a respective keep out zone (KOZ), a union of the respective KOZs defining an overall KOZ for the plurality of TSVs; and

forming a plurality of TSV stress plugs at a perimeter of the overall KOZ of the plurality of TSVs, wherein none of the plurality of active devices are located within the overall KOZ;

wherein the plurality of TSVs form a circle and the plurality of TSV stress plugs are formed at alternating positions within the circle.