Semiconductor structure having contact plug and method of making the same
First Claim
1. A semiconductor structure having at least a contact plug, comprising:
- a substrate;
a transistor disposed on the substrate, wherein the transistor comprises a gate and a source/drain region;
a first inter-layer dielectric (ILD) layer disposed on the transistor, wherein a bottom surface of the first ILD layer is level with a top surface of the gate;
a first contact plug disposed in the first ILD layer to electrically connect the source/drain region, wherein a top surface of the first contact plug is higher than a top surface of the gate;
a second ILD layer disposed on the first ILD layer;
a second contact plug disposed in the second ILD layer to electrically connect the first contact plug, wherein a bottom surface of the second contact plug is level with a top surface of the first ILD layer; and
a third contact plug disposed in the first ILD layer and the second ILD layer to electrically connect the gate.
1 Assignment
0 Petitions
Accused Products
Abstract
The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.
-
Citations
10 Claims
-
1. A semiconductor structure having at least a contact plug, comprising:
-
a substrate; a transistor disposed on the substrate, wherein the transistor comprises a gate and a source/drain region; a first inter-layer dielectric (ILD) layer disposed on the transistor, wherein a bottom surface of the first ILD layer is level with a top surface of the gate; a first contact plug disposed in the first ILD layer to electrically connect the source/drain region, wherein a top surface of the first contact plug is higher than a top surface of the gate; a second ILD layer disposed on the first ILD layer; a second contact plug disposed in the second ILD layer to electrically connect the first contact plug, wherein a bottom surface of the second contact plug is level with a top surface of the first ILD layer; and a third contact plug disposed in the first ILD layer and the second ILD layer to electrically connect the gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
Specification