Semiconductor devices having fin structures and fabrication methods thereof

• US 9,054,219 B1
• Filed: 02/05/2014
• Issued: 06/09/2015
• Est. Priority Date: 08/05/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Hoffmann, Thomas, Thompson, Scott E.
• Primary Examiner(s): Ahmadi, Mohsen
• Application Number:
  US14/173,570
• Time in Patent Office: 489 Days
• Field of Search: 438/154, 438/275, 438/283, 438/308, 438/481, 438/527, 257/E21.63, 257/E21.409
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A method of fabricating semiconductor devices includes providing a semiconducting substrate. The method also includes defining a heavily doped region at a surface of the semiconducting substrate in at least one area of the semiconducting substrate, where the heavily doped region includes a heavily doped layer having a doping concentration greater than a doping concentration of the semiconducting substrate. The method also includes forming an additional layer of semiconductor material on the semiconducting substrate, the additional layer comprising a substantially undoped layer. The method further includes applying a first removal process to the semiconducting substrate to define an unetched portion and an etched portion, where the unetched portion defines a fin structure, and the etched portion extends through the additional layer, and then isolating the fin structure from other structures.

Claims

1. A method of fabricating semiconductor devices, comprising:

providing a silicon substrate;

forming a heavily doped region at a surface of the silicon substrate in at least one area of the silicon substrate, the heavily doped region comprising at least one heavily doped layer, the at least one heavily doped layer having a doping concentration greater than a doping concentration of the silicon substrate and of a first conductivity type;

forming an additional layer on the silicon substrate, the additional layer comprising a substantially undoped epitaxial silicon layer;

applying a first removal process to the silicon substrate to define at least one unetched portion and at least one etched portion in the at least one area, the at least one unetched portion defining at least one fin structure, and the at least one etched portion extending through at least the thickness of the additional layer and into the heavily doped layer;

forming a dielectric in the at least one etched portion with a thickness selected so that the additional layer in the at least one fin structure remains exposed; and

forming a gate that wraps around the exposed surfaces of the at least one fin structure,

wherein forming the heavily doped region comprises providing additional implants to provide a surface layer at the interface between the heavily doped region and the additional layer to prevent diffusion of dopants from the heavily doped region to the additional layer.

2. The method of claim 1, further comprising:

prior to applying the first removal process, providing a stop layer on the additional layer in a pattern corresponding to the at least one fin structure; and

subsequent to applying the first removal process, depositing a blanket dielectric film on the silicon substrate, and

wherein the forming of the dielectric comprises applying a planarization process to the semiconductor substrate so that a planarized surface of the blanket dielectric film coincides substantially with the stop layer and applying a second removal process to the semiconducting substrate that preferentially removes the blanket dielectric film over other materials.

3. The method of claim 1, wherein forming the heavily doped region comprises implanting at least one species for providing dopant atoms of the first conductivity type to a concentration of about 5×

10¹⁸ to 1×

10²⁰ atoms/cm³.

4. The method of claim 1, wherein the silicon substrate comprises one of a bulk silicon substrate, an epi substrate, or a silicon-on-insulator substrate.

5. A method of fabricating semiconductor devices, comprising:

providing a silicon substrate;

forming a heavily doped region at a surface of the silicon substrate in at least one area of the silicon substrate using ion implantation, the heavily doped region comprising at least one heavily doped layer, the at least one heavily doped layer having a doping concentration greater than a doping concentration of the semiconducting substrate and of a first conductivity type;

forming an additional layer of semiconductor material on the silicon substrate, the additional layer comprising a substantially undoped silicon-comprising epitaxial layer;

applying a first removal process to the silicon substrate to define at least one unetched portion and at least one etched portion in the at least one area, the at least one unetched portion defining at least one fin structure, and the at least one etched portion extending through at least a portion of the heavily doped region;

disposing at least one dielectric layer in the at least one etched portion, the thickness of the at least one dielectric layer selected to so that the upper surface of the at least one dielectric layer abuts the heavily doped region; and

forming a gate in the at least fin structure to provide at least one FinFET device,

wherein forming the heavily doped region comprises providing additional implants to provide a surface layer at the interface between the heavily doped region and the additional lam to prevent diffusion of dopants from the heavily doped region to the additional layer.

6. The method of claim 5, further comprising:

prior to applying the first removal process, providing a stop layer on the additional layer in a pattern corresponding to the at least one fin structure; and

subsequent to applying the first removal process, depositing at least one blanket dielectric film on the silicon substrate, and

wherein the disposing further comprises applying a planarization process to the silicon substrate so that a planarized surface of the at least one blanket dielectric film coincides substantially with the stop layer and applying a second removal process to the silicon substrate that preferentially removes a portion of the at least one blanket dielectric film over other materials to yield the at least one dielectric layer.

7. The method of claim 5, wherein forming the heavily doped region comprises implanting at least one species for providing dopant atoms of the first conductivity type.

8. The method of claim 5, wherein the silicon substrate comprises one of a bulk silicon substrate, an epi substrate, or a silicon-on-insulator substrate.

9. The method of claim 5, wherein substantially undoped silicon-comprising epitaxial layer comprises a substantially undoped silicon-comprising epitaxial layer.

10. A method of fabricating semiconductor devices, comprising:

providing a silicon substrate;

forming a heavily doped region at a surface of the silicon substrate in at least one area of the semiconducting substrate using ion implantation, the heavily doped region comprising at least one heavily doped layer, the at least one heavily doped layer having a doping concentration greater than a doping concentration of the semiconducting silicon substrate and of a first conductivity type;

forming an additional layer of semiconductor material on the silicon substrate, the additional layer comprising a substantially undoped epitaxial silicon layer;

applying a first removal process to the silicon substrate to define at least one first unetched portion, at least one second unetched portion, and at least one etched portion in the at least one area, the at least one first unetched portion defining at least one fin structure, the at least one second unetched portion defining at least one planar active area, and the at least one etched portion extending through at least through a portion of the heavily doped layer;

forming at least one dielectric layer in the at least one etched portion so that an upper surface of the at least one dielectric layer abuts the heavily doped region in the at least one fin structure and abuts an upper surface of the additional layer in the at least one planar active area; and

forming a gate in the at least one fin structure to provide at least one FinFET device; and

forming a gate in the at least one planar active region to provide at least one planar MOSFET device,

wherein forming the heavily doped region comprises providing additional implants to provide a surface layer at the interface between the heavily doped region and the additional layer to prevent diffusion of dopants from the heavily doped region to the additional layer.

11. The method of claim 10, wherein the at least one etched portion extends through the heavily doped region.

12. The method of claim 10, further comprising:

prior to applying the first removal process, providing a stop layer on the additional layer in a pattern corresponding to the at least one fin structure and the at least one planar active area;

subsequent to applying the first removal process, depositing at least one blanket dielectric film on the silicon substrate; and

wherein the disposing comprises applying a planarization process to the silicon substrate so that a planarized surface of the at least one blanket dielectric film coincides substantially with the stop layer, forming a masking layer over the at least planar active area and adjoining portions of the planarized surface, and applying a second removal process to the silicon substrate that preferentially removes a portion of the at least one blanket dielectric film over other materials to yield the at least one dielectric layer.

13. The method of claim 10, wherein forming the heavily doped region comprises implanting at least one species for providing dopant atoms of the first conductivity type.

14. The method of claim 10, wherein forming the heavily doped region comprises implanting at least one species for providing at least one threshold voltage adjustment layer for the at least one planar MOSFET device.