Method of fabricating semiconductor device using gang bonding and semiconductor device fabricated by the same

• US 9,054,231 B2
• Filed: 06/30/2011
• Issued: 06/09/2015
• Est. Priority Date: 12/10/2010
• Status: Active Grant

• Current Assignee: Chung Hoon Lee, Dae Sung Kal, Ki Bum Nam
• Original Assignee: Chung Hoon Lee, Dae Sung Kal, Ki Bum Nam
• Inventors: Lee, Chung Hoon, Kal, Dae Sung, Nam, Ki Bum
• Primary Examiner(s): LUKE, DANIEL M
• Application Number:
  US13/992,941
• Publication Number:
  US 20130264600A1
• Time in Patent Office: 1,440 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/06151 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/16013 the bump connector being larger than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/16057 in side view
• CPC Class Codes: H01L 2224/16151 the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
• CPC Class Codes: H01L 2224/27462 Electroplating
• CPC Class Codes: H01L 2224/32238 the layer connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/325 Material
• CPC Class Codes: H01L 2224/33151 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81893 Anodic bonding, i.e. bonding by applying a voltage across the interface in order to induce ions migration leading to an irreversible chemical bond
• CPC Class Codes: H01L 2224/83447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/83455 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/83893 : Anodic bonding, i.e. bonding by applying a voltage across the interface in order to induce ions migration leading to an irreversible chemical bond
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/49805 : the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2933/0033 : relating to semiconductor body packages
• CPC Class Codes: H01L 33/005 : Processes
• CPC Class Codes: H01L 33/0093 : Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 : Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/36 : characterised by the electrodes
• CPC Class Codes: H01L 33/44 : characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/50 : Wavelength conversion elements
• CPC Class Codes: H01L 33/507 : the elements being in intimate contact with parts other than the semiconductor body or integrated with parts other than the semiconductor body

Abstract

A method of fabricating a semiconductor device using gang bonding and a semiconductor device fabricated by the same, the method comprising preparing a support substrate having a plurality of semiconductor stack structures aligned on a top thereof. Each of the semiconductor stack structures comprises a first conductive semiconductor layer, a second conductive semiconductor layer and an active region interposed between the first and second conductive semiconductor layers. A member having first lead electrodes and second lead electrodes is prepared to correspond to the plurality of semiconductor stack structures. Then, the semiconductor stack structures are bonded to the member while maintaining the semiconductor stack structures on the support substrate. After the semiconductor stack structures are bonded to the member, the member is divided.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a plurality of semiconductor stack structures on a first surface of a support substrate, wherein each of the semiconductor stack structures comprises a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers;

forming a member comprising a plurality of first lead electrodes and second lead electrodes, wherein a first and second lead electrode of the plurality of first and second lead electrodes respectively corresponds to a semiconductor stack structure of the plurality of semiconductor stack structures;

bonding the plurality of semiconductor stack structures to the member while maintaining the plurality of semiconductor stack structures on the support substrate;

dividing the member after the plurality of semiconductor stack structures are bonded to the member; and

forming a plurality of first and second electrodes on the semiconductor stack structures, wherein a first and second electrode of the plurality of first and second electrodes are electrically connected to the first and second conductive semiconductor layers of each of the semiconductor stack structures, respectively, and wherein the first electrodes are electrically connected to one another on the support substrate, and the second electrodes are electrically connected to one another on the support substrate.

2. The method of claim 1, wherein the first and second conductive semiconductor layers of each of the semiconductor stack structures are electrically connected to the corresponding first and second lead electrodes respectively by bonding the plurality of semiconductor stack structures to the member.

3. The method of claim 2,

wherein the first and second electrodes are bonded to the first and second lead electrodes, respectively.

4. The method of claim 3, wherein each of the first and second electrodes comprises an electrode pad and an additional electrode.

5. The method of claim 3, wherein the member further comprises a plurality of spacer electrodes, wherein spacer electrodes of the plurality of spacer electrodes are respectively formed on the first and second lead electrodes.

6. The method of claim 5, wherein the first and second electrodes are respectively bonded to the spacer electrodes using an electroplating bonding technique.

7. The method of claim 1, wherein the plurality of semiconductor stack structures are bonded to the lead electrodes using a conductive adhesive.

8. The method of claim 1, wherein the plurality of stack structures are bonded to the lead electrodes using an electroplating bonding technique.

9. The method of claim 1, wherein the first lead electrodes are electrically connected to one another, and the second lead electrodes are electrically connected to one another.

10. The method of claim 1, further comprising:

forming a first wavelength converter comprising a uniform thickness on a surface of the semiconductor stack structures opposite to the member, after the plurality of semiconductor stack structures are bonded to the member.

11. The method of claim 10, wherein the support substrate comprises a growth substrate, and the first wavelength converter is formed on the growth substrate.

12. The method of claim 11, wherein when the member is divided, the support substrate is divided together with the member.

13. The method of claim 11, further comprising:

removing the support substrate before the first wavelength converter is formed.

14. The method of claim 10, further comprising:

forming second wavelength converter on the support substrate, the second wavelength converter covering at least side surfaces of the plurality of semiconductor stack structures.

15. The method of claim 10, further comprising:

disposing a resin molding portion in a space between the support substrate and the member, wherein the resin molding portion comprises a phosphor.

16. The method of claim 15, wherein the first wavelength converter is formed at the same time as the resin molding portion.

17. The method of claim 10, wherein the support substrate comprises a carrier substrate comprising a plurality of semiconductor chips bonded thereto, and each of the semiconductor chips comprises a semiconductor stack structure of the plurality of the semiconductor stack structures.

18. The method of claim 17, wherein each of the semiconductor chips further comprises a second wavelength converter that covers at least side surfaces of the semiconductor stack structure.

19. The method of claim 17, further comprising:

removing the carrier substrate after the semiconductor stack structures are bonded to the member; and

disposing a second wavelength converter in a space among the plurality of semiconductor chips,

wherein the first wavelength converter is formed at the same time as the second wavelength converter.

20. The method of claim 1, wherein bonding the plurality of semiconductor stack structures is performed at a temperature of about 100°

C. or lower.

21. The method of claim 1, wherein the semiconductor device comprises a light emitting diode (LED) package.