Single instruction processing of network packets

• US 9,054,987 B2
• Filed: 06/25/2013
• Issued: 06/09/2015
• Est. Priority Date: 12/30/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Veal, Bryan E., Schluessler, Travis T.
• Primary Examiner(s): PHUNKULH, BOB A
• Application Number:
  US13/926,085
• Publication Number:
  US 20140036909A1
• Time in Patent Office: 714 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element

Abstract

Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.

Claims

1. A method comprising:

providing a single instruction/multiple data (SIMD) program to process a first vector of data wherein each element of the first vector corresponds to a different received packet;

the program comprising instructions which, when executed, cause SIMD processing comprising;

accessing a second vector, wherein each element of the second vector identifies occupancy of a corresponding element in the first vector;

accessing a third vector, wherein each element of the third vector comprises flow state data for a flow of an associated packet in the first vector; and

modifying elements in the third vector; and

wherein the first vector comprises a vector that is not fully occupied and the flow state data comprises Transmission Control Protocol (TCP) flow state data.

2. The method of claim 1,

wherein each element of the vector corresponds to a same strict subset of packet header fields.

3. The method of claim 1, further comprising instructions which when executed, cause SIMD processing comprising:

determining a packet should not be processed by the SIMD instructions.

4. The method of claim 1, wherein the SIMD program comprises at least a portion of the program to perform at least one of the following:

determine protocols of the packets;

validate the packets;

compute header values for the packets; and

determine an execution unit to handle the packets.

5. A network interface controller, comprising:

an interface to a PHY;

a Direct Memory Access (DMA) engine to transfer data from the network interface controller to and from a memory;

circuitry to arrange data of the packets into a vector, wherein each element of the vector corresponds to a different packet, for single instruction/multiple data (SIMD) processing of the vector;

wherein the circuitry to arrange data of the packets into a vector comprises circuitry to arrange data of the packets into a vector where each element of the vector corresponds to the same strict subset of packet header fields, wherein the packets comprising Internet Protocol (IP) packets.

6. The network interface controller of claim 5, further comprising circuitry to assign packets to the vector such that the vector includes elements corresponding to multiple packets belonging to the same flow.

7. The network interface controller of claim 5, further comprising circuitry to assign packets to the vector such that the vector does not include elements corresponding to multiple packets belonging to the same flow.

8. A computer program disposed on a non-transitory computer readable medium comprising instructions for causing circuitry to:

access a vector of network packet data, individual vector elements comprising a strict subset of fields of a network packet header, respective vector elements corresponding to different respective network packets; and

cause single instruction, parallel processing of the respective vector elements corresponding to the different respective network packets; and

wherein the network packets comprise Internet Protocol packets.

9. The program of claim 8, wherein the single instruction, parallel processing of the respective vector elements comprises a forwarding lookup.

10. The program of claim 8, wherein the single instruction, parallel processing of the respective vector elements comprises a hash based on data included in the strict subset of fields of the respective network packet header.

11. The program of claim 8, wherein the network packet header comprises a Transmission Control Protocol (TCP) segment header.

12. The program of claim 8, wherein the network packet header comprises an Internet Protocol (IP) datagram header.

13. The program of claim 8, wherein strict subset of fields comprise a field from an Internet Protocol (IP) datagram header.

14. The program of claim 8, wherein the vector elements comprise vector elements in contiguous memory locations.

15. The program of claim 8, wherein the instructions to cause single instruction, parallel processing of the respective vector elements comprise instructions to cause single instruction, parallel processing of the respective vectors for a vector that is not fully populated.

16. The program of 8, wherein the single instruction, parallel processing of the respective array elements comprises updating of flow state data associated with the respective network packets.

17. The program of claim 16, wherein the flow state data comprises an array of flow state data, where respective elements of the array of flow state data correspond to the respective network packets of the array of network packet data.

18. A system comprising:

at least one processor capable of single instruction, parallel processing of vector elements;

logic, when in operation, to;

access a vector of network packet data, individual vector elements comprising a strict subset of fields of a network packet header, respective vector elements corresponding to different respective network packets; and

cause single instruction, parallel processing by the at least one processor of the respective vector elements corresponding to the different respective network packets;

wherein the network packets comprise Internet Protocol packets.

19. The system of claim 18, wherein the single instruction, parallel processing of the respective vector elements comprises a forwarding lookup.

20. The system of claim 18, wherein the single instruction, parallel processing of the respective vector elements comprises a hash based on data included in the strict subset of fields.

21. The system of claim 18, wherein the at least one network packet header comprises an Internet Protocol (IP) datagram header.

22. The program of claim 18, wherein the vector elements comprise vector elements in contiguous memory locations.

23. The program of claim 18, wherein the logic to cause single instruction, parallel processing of the respective vector elements comprises logic to cause single instruction, parallel processing of the respective vectors for a vector that is not fully populated.