Selective posted data error detection based on request type

• US 9,058,178 B2
• Filed: 02/26/2013
• Issued: 06/16/2015
• Est. Priority Date: 11/16/2012
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cargnoni, Robert A., Dodson, John S., Guthrie, Guy L., Starke, William J., Stuecheli, Jeffrey A.
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US13/777,729
• Publication Number:
  US 20140143613A1
• Time in Patent Office: 840 Days
• Field of Search: 714/48, 714/49, 714/54, 714/47.1
• US Class Current: 1/1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification

Abstract

In a data processing system, a selection is made, based at least on an access type of a memory access request, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request. In response to receipt of the memory access request and selection of the first timing, data from the target memory block is transmitted to a requestor prior to completion of error detection processing on the target memory block. In response to receipt of the memory access request and selection of the second timing, data from the target memory block is transmitted to the requestor after and in response to completion of error detection processing on the target memory block.

Claims

1. A method of data processing, comprising:

in response to receiving a memory access request, selecting, based at least on an access type specified by the memory access request, between at least a first timing and a second timing of data transmission with respect to completion of error detection processing on a target memory block of the memory access request;

performing error detection processing on the target memory block, wherein performing error detection processing includes performing error detection processing utilizing a same error detection technique for both the first and second timings;

in response to receipt of the memory access request and selection of the first timing, transmitting data from the target memory block to a requestor prior to completion of the error detection processing on the target memory block; and

in response to receipt of the memory access request and selection of the second timing, transmitting data from the target memory block to the requestor after and in response to completion of the error detection processing on the target memory block.

2. The method of claim 1, wherein the selecting includes selecting the first timing for the memory access request based on the memory access request being one of a set including a demand data load request generated by execution of a load-type instruction and a data prefetch request.

3. The method of claim 1, wherein the selecting includes a memory subsystem selecting between at least the first timing and the second timing.

4. The method of claim 1, wherein the selecting further includes selecting between the first timing and the second timing based at least on addresses of previously detected errors in a memory subsystem.

5. The method of claim 1, and further comprising:

a memory subsystem sending, in association with the target memory block, a posted status indicator of a timing of data transmission with respect to completion of error detection processing on the target memory block.

6. The method of claim 4, and further comprising handling the target memory block in a processor core based on a timing indicated by the posted status indicator.

7. The method of claim 1, and further comprising:

in response to receipt of the memory access request and selection of the first timing, transmitting a data error indicator indicating whether or not the target memory block has a data error.

8. The method of claim 7, wherein:

the requestor comprises a processor core;

the method further comprises;

in the processor core, speculatively finishing execution of one or more instructions that are dependent on the target memory block prior to receipt of the data error indicator; and

completing the one or more instructions in response to the data error indicator.

9. The method of claim 7, wherein:

transmitting data includes transmitting granules of the target memory block at intervals; and

transmitting the data error indicator includes transmitting the data error indicator with one of the granules other than a first granule.

10. The method of claim 1, and further comprising:

in response to detection of an error in the target memory block, the requestor reissuing the memory access request with the first timing disabled.