Retirement serialisation of status register access operations

• US 9,058,179 B2
• Filed: 11/12/2010
• Issued: 06/16/2015
• Est. Priority Date: 11/12/2010
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Hardage, James Nolan
• Primary Examiner(s): Giroux, George
• Application Number:
  US12/926,374
• Publication Number:
  US 20120124340A1
• Time in Patent Office: 1,677 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

A processor 2 for performing out-of-order execution of a stream of program instructions includes a special register access pipeline for performing status access instructions accessing a status register 20. In order to serialise these status access instructions relative to other instructions within the system access timing control circuitry 32 permits dispatch of other instructions to proceed but controls the commit queue and the result queue such that no program instructions in program order succeeding the status access instruction are permitted to complete until after a trigger state has been detected in which all program instructions preceding in program order the status access instruction have been performed and made any updates to the architectural state. This is followed by the performance of the status access instruction itself.

Claims

1. Apparatus for executing a stream of program instructions, said apparatus comprising:

a plurality of processing pipelines including a special register pipeline configured to respond to a status access instruction to perform a status register access operation to a status register configured to store at least one state variable;

dispatch queue circuitry configured to store a dispatch queue of undispatched program instructions awaiting dispatch to one of said plurality of pipelines and to dispatch said status access instruction to said special register pipeline;

commit queue circuitry configured to store a commit queue of uncommitted program instructions awaiting a determination to be permitted to complete processing;

result queue circuitry configured to store a result queue of unretired program instructions yet to update architectural state variables; and

access timing control circuitry coupled to said special register pipeline, said commit queue circuitry and said result queue circuitry, said access timing control circuitry being configured such that, when said status access instruction is issued to said special register pipeline and while program instructions continue to be dispatched from said dispatch queue, said access timing control circuitry;

(i) controls said commit queue circuitry such that no program instruction succeeding in program order said status access instruction within said stream of program instructions is permitted to complete processing;

(ii) detects from said result queue circuitry a trigger state when all program instructions preceding in program order said status access instruction within said stream of program instructions have performed any updates to architectural state variables of said apparatus; and

(iii) upon detection of said trigger state, triggers said special register pipeline to perform said status register access operation, comprising special register issue queue circuitry, each entry within said special register issue queue circuitry including an issue policy field for storing an issue policy value specifying one of a plurality of issue politics to be applied to issuing of a program instruction corresponding to said entry to said special register pipeline.

2. Apparatus as claimed in claim 1, wherein, after said special register pipeline has performed said status register access operation, said access timing control circuitry then permits said program instruction succeeding in program order said status access instruction within said stream of program instructions to complete processing.

3. Apparatus as claimed in claim 1, wherein said status register is a current program status register storing a program status value set by execution of program instructions preceding in program order said status access instruction within said stream of program instructions.

4. Apparatus as claimed in claim 1, comprising a commit pointer register configured to store a commit pointer indicating an oldest uncommitted program instruction within said commit queue.

5. Apparatus as claimed in claim 4, wherein an entry within said commit queue for said status access instruction includes a marker flag and said access timing control circuitry detects when said commit pointer indicates said entry including said marker flag to determine when there are no uncommitted program instructions preceding in program order said status access instruction and then stall said commit queue circuitry.

6. Apparatus as claimed in claim 4, comprising a retirement pointer register configured to store a retirement pointer indicating an oldest unretired program instructions.

7. Apparatus as claimed in claim 6, wherein said access timing control circuitry detects when said retirement pointer matches said commit pointer as indicating said trigger state.

8. Apparatus as claimed in claim 1, wherein said plurality of issue policies comprise at least one of:

(i) an early policy whereby a program instruction issues when all source operands for said program instruction are valid;

(ii) a committed policy whereby a program instruction issues when said program instruction is committed for completion and all source operands for said program instruction are valid; and

(iii) an oldest unretired policy whereby a program instruction issues when all program instruction preceding in program order said program instruction within said stream of program instructions have performed any updates to architectural state variables of said apparatus and all source operands for said program instruction are valid.

9. Apparatus as claimed in claim 1, wherein said access timing control circuitry is formed of a plurality portions located at different positions within said apparatus.

10. Apparatus for executing a stream of program instructions, said apparatus comprising:

a plurality of processing pipelines means for performing processing operations, said plurality of processing pipeline means including a special register pipeline means for performing a status register access operation to a status register means for storing at least one state variable, said status register access operation being performed in response to a status access instruction;

dispatch queue means for storing a dispatch queue of undispatched program instructions awaiting dispatch to one of said plurality of pipelines means and for dispatching said status access instruction to said special register pipeline means;

commit queue means for storing a commit queue of uncommitted program instructions awaiting a determination to be permitted to complete processing;

result queue means for storing a result queue of unretired program instructions yet to update architectural state variables; and

access timing control means for controlling access timing, said access timing control means being coupled to said special register pipeline means, said commit queue means and said result queue means, and said access timing control means being configured such that, when said status access instruction is issued to said special register pipeline means and while program instructions continue to be dispatched from said dispatch queue means, said access timing control means;

(i) controls said commit queue means such that no program instruction succeeding in program order said status access instruction within said stream of program instructions is permitted to complete processing;

(ii) detects from said result queue means a trigger state when all program instructions preceding in program order said status access instruction within said stream of program instructions have performed any updates to architectural state variables of said apparatus; and

(iii) upon detection of said trigger state, triggers said special register pipeline means to perform said status register access operation, comprising special register issue queue means, each entry within said special register issue queue means including an issue policy field for storing an issue policy value specifying one of a plurality of issue policies to be applied to issuing of a program instruction corresponding to said entry to said special register pipeline.

11. A method of executing a stream of program instructions, said method comprising the steps of:

performing processing operations using a plurality of processing pipelines, said plurality of processing pipelines including a special register pipeline configured to perform a status register access operation to a status register configured to store at least one state variable, said status register access operation being performed in response to a status access instruction;

storing a dispatch queue of undispatched program instructions awaiting dispatch to one of said plurality of pipelines and dispatching said status access instruction from said dispatch queue to said special register pipeline;

storing a commit queue of uncommitted program instructions awaiting a determination to be permitted to complete processing;

storing a result queue of unretired program instructions yet to update architectural state variables; and

controlling access timing, when said status access instruction is issued to said special register pipeline and while program instructions continue to be dispatched from said dispatch queue, by;

(i) controlling said commit queue such that no program instruction succeeding in program order said status access instruction within said stream of program instructions is permitted to complete processing;

(ii) detecting from said result queue a trigger state when all program instructions preceding in program order said status access instruction within said stream of program instructions have performed any updates to architectural state variables; and

(iii) upon detection of said trigger state, triggering said special register pipeline to perform said status register access operation, comprising strong entries within a special register issue queue circuitry, each entry including an issue policy field for storing an issue policy value specifying one of a plurality of issue policies to be applied to issuing of a program instruction corresponding to said entry to said special register pipeline.

12. A method as claimed in claim 11, wherein, after said special register pipeline has performed said status register access operation, said step of controlling access timing then permits said program instruction succeeding in program order said status access instruction within said stream of program instructions to complete processing.

13. A method as claimed in claim 11, wherein said status register is a current program status register storing a program status value set by execution of program instructions preceding in program order said status access instruction within said stream of program instructions.

14. A method as claimed in claim 11, comprising storing a commit pointer indicating an oldest uncommitted program instruction within said commit queue.

15. A method as claimed in claim 14, wherein an entry within said commit queue for said status access instruction includes a marker flag and said step of controlling access timing detects when said commit pointer indicates said entry including said marker flag to determine when there are no uncommitted program instructions preceding in program order said status access instruction and then stall said commit queue.

16. A method as claimed in claim 14, comprising storing a retirement pointer indicating an oldest unretired program instructions.

17. A method as claimed in claim 16, wherein said step of controlling access timing detects when said retirement pointer matches said commit pointer as indicating said trigger state.

18. A method as claimed in claim 11, wherein said plurality of issue policies comprise at least one of:

(i) an early policy whereby a program instruction issues when all source operands for said program instruction are valid;

(ii) a committed policy whereby a program instruction issues when said program instruction is committed for completion and all source operands for said program instruction are valid; and

(iii) an oldest unretired policy whereby a program instruction issues when all program instruction preceding in program order said program instruction within said stream of program instructions have performed any updates to architectural state variables of said apparatus and all source operands for said program instruction are valid.