Transient condition management utilizing a posted error detection processing protocol

• US 9,058,260 B2
• Filed: 04/04/2013
• Issued: 06/16/2015
• Est. Priority Date: 04/04/2013
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dodson, John S., Goodman, Benjiman L., Guthrie, Guy L., Retter, Eric E., Starke, William J., Stuecheli, Jeffrey A.
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US13/856,937
• Publication Number:
  US 20140304573A1
• Time in Patent Office: 803 Days
• Field of Search: 714/807, 714/15, 714/16, 714/17, 714/6.1
• US Class Current: 1/1
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00

Abstract

In a data processing system, a memory subsystem detects whether or not at least one potentially transient condition is present that would prevent timely servicing of one or more memory access requests directed to the associated system memory. In response to detecting at least one such potentially transient condition, the memory system identifies a first read request affected by the at least one potentially transient condition. In response to identifying the read request, the memory subsystem signals to a request source to issue a second read request for the same target address by transmitting to the request source dummy data and a data error indicator.

Claims

1. A memory subsystem for controlling access to a system memory of a data processing system, the memory subsystem comprising:

error detection circuitry; and

control logic that;

detects whether or not at least one potentially transient condition is present that would prevent timely servicing of one or more memory access requests directed to the associated system memory;

in response to detecting at least one potentially transient condition that would prevent timely servicing of one or more memory access requests directed to the associated system memory, identifies a first read request affected by the at least one potentially transient condition, wherein the first read request specifies a target address; and

in response to identifying the read request, transmits, to a request source, dummy data and a data error indicator to indicate to the request source to issue a second read request for the target address.

2. The memory subsystem of claim 1, wherein the at least one potentially transient condition is an address error.

3. The memory subsystem of claim 1, wherein the at least one potentially transient condition is a memory refresh cycle.

4. The memory subsystem of claim 1, wherein the at least one potentially transient condition is a hang condition.

5. The memory subsystem of claim 1, wherein:

the memory subsystem transmits granules of the dummy data at intervals; and

the memory subsystem transmits the data error indicator with one of the granules other than a first granule.

6. The method of claim 1, wherein:

the first read request indicates posted error detection processing is enabled for the first request; and

the second read request indicates posted error detection processing is disabled for the second request.

7. A data processing system comprising:

the memory subsystem of claim 1; and

a processor core coupled to the memory subsystem, wherein the processor core is the request source.

8. The data processing system of claim 7, wherein the processor core includes:

an execution unit that speculatively finishes execution of one or more instructions that are dependent on the first read request prior to receipt of the data error indicator; and

completion logic that flushes the one or more instructions in response to the data error indicator.

9. A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a memory subsystem of a data processing system, including;

error detection circuitry; and

control logic that;

detects whether or not at least one potentially transient condition is present that would prevent timely servicing of one or more memory access requests directed to the associated system memory;

in response to detecting at least one potentially transient condition that would prevent timely servicing of one or more memory access requests directed to the associated system memory, identifies a first read request affected by the at least one potentially transient condition, wherein the first read request specifies a target address; and

in response to identifying the read request, transmits, to a request source, dummy data and a data error indicator to indicate to the request source to issue a second read request for the target address.

10. The design structure of claim 9, wherein the design structure comprises a hardware description language (HDL) design structure.