System and method for LCD loop control

• US 9,058,761 B2
• Filed: 06/30/2009
• Issued: 06/16/2015
• Est. Priority Date: 06/30/2009
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Piasecki, Douglas, David, Thomas S., Rueger, Timothy Thomas, Mastovich, Stefan, Liu, Jia-Hau
• Primary Examiner(s): Mengistu, Amare
• Assistant Examiner(s): Nadkarni, Sarvesh J
• Application Number:
  US12/495,564
• Publication Number:
  US 20100328295A1
• Time in Patent Office: 2,177 Days
• Field of Search: 345/212, 345/204, 345/87
• US Class Current: 1/1
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/04 for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions

Abstract

An LCD controller includes a charge pump for generating a charge voltage responsive to an external voltage and a clock signal. The controller further includes an oscillator for generating the clock signal responsive to an oscillator control signal. An LCD driver voltage circuit generates a plurality of LCD driver voltages for driving segments of an associated LCD display. A loop control circuit within the LCD controller monitors an LCD driver voltage from the LCD driver voltage circuit and generates the oscillator control signal responsive thereto to enable and disable the oscillator.

Claims

1. An LCD controller, comprising:

a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal;

an oscillator for generating the clock signal responsive to an oscillator control signal;

an LCD driver voltage circuit for generating a plurality of LCD driver voltages for driving segments of an LCD display; and

loop control circuit for monitoring an LCD driver voltage from the LCD driver voltage circuit and generating the oscillator control signal responsive thereto to enable and disable the oscillator by using a latch, the loop control circuit further comprising;

a comparator for comparing the LCD driver voltage with a reference voltage and generating an output at a first logical level when the LCD driver voltage exceeds the reference voltage by a first predetermined level and generating the output at a second logical level when the LCD driver voltage falls below the reference voltage by a second predetermined level;

wherein the latch latches the output at either the first logical level or the second logical level; and

control logic for generating the oscillator control signal to enable the oscillator responsive to the output at the second logical level and for generating the oscillator control signal to disable the oscillator responsive to the output at the first logical level.

2. The LCD controller of claim 1, wherein the loop control circuit generates the oscillator control signal to enable the oscillator responsive to the LCD driver voltage falling below a first predetermined voltage level and generates the oscillator control signal to disable the oscillator responsive to the LCD driver rising above a second predetermined voltage level.

3. The LCD controller of claim 1, wherein the LCD driver voltage circuit further comprises a voltage divider including a plurality of resistors in series, wherein each of the plurality of voltages are provided from a point on the resistor divider.

4. The LCD controller of claim 1, wherein the loop control circuit further comprises:

a multiplexer for selecting the LCD driver voltage from the LCD driver voltage circuit; and

a contrast control circuit for controlling the selection of the LCD driver voltage by the multiplexer.

5. The LCD controller of claim 1, wherein the control logic further enables/disables the LCD display responsive to an enable control signal.

6. The LCD controller of claim 1, further including a bandgap generator for generating the reference voltage.

7. An LCD controller, comprising:

a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal;

an oscillator for generating the clock signal responsive to an oscillator control signal;

an LCD driver voltage circuit for generating a plurality of LCD driver voltages for driving segments of an LCD display, the LCD driver voltage circuit further including a voltage divider including a plurality of resistors in series, wherein each of the plurality of voltages are provided from a point on the resistor divider;

a comparator for comparing an LCD driver voltage with a reference voltage and generating an output at a first logical level when the LCD driver voltage exceeds the reference voltage by a first predetermined level and generating the output at a second logical level when the LCD driver voltage falls below the reference voltage by a second predetermined level, wherein the reference voltage is generated by using a bandgap generator;

a latch for latching the output at either the first logical level or the second logical level; and

control logic for generating the oscillator control signal to enable the oscillator responsive to the output at the second logical level and for generating the oscillator control signal to disable the oscillator responsive to the output at the first logical level.

8. The LCD controller of claim 7, further comprising:

a multiplexer for selecting the LCD driver voltage from the LCD driver voltage circuit; and

a contrast control circuit for controlling the selection of the LCD driver voltage by the multiplexer.

9. The LCD controller of claim 7, wherein the control logic further enables/disables the LCD display responsive to an enable control signal.

10. The LCD controller of claim 7, further including a bandgap generator for generating the reference voltage.

11. A method for generating an LCD display driver voltage from an LCD controller, comprising the steps of:

generating a charge voltage responsive to an external voltage and a clock signal;

generating a plurality of LCD driver voltages for driving segments of an LCD display responsive to the charge voltage;

monitoring an LCD driver voltage;

generating an oscillator control signal responsive to the monitored LCD driver voltage; and

controlling operation of an oscillator responsive to the oscillator control signal to generate the clock signal by using a latch, wherein generating the oscillator control signal further comprises;

comparing the LCD driver voltage with a reference voltage;

generating an output at a first logical level when the LCD driver voltage exceeds the reference voltage by a first predetermined level;

using the latch to latch the output at either the first logical level; and

generating the oscillator control signal to disable the oscillator responsive to the output at the first logical level.

12. The method of claim 11, wherein the step of generating an oscillator control signal further comprises the steps of:

generating the oscillator control signal to enable the oscillator responsive to the LCD driver voltage falling below a first predetermined voltage level; and

generating the oscillator control signal to disable the oscillator responsive to the LCD driver rising above a second predetermined voltage level.

13. The method of claim 11, wherein the step of generating a plurality of LCD driver voltages further comprises the step of outputting a voltage from a point on a voltage divider circuit.

14. The method of claim 11, wherein the step of monitoring further comprises the steps of:

multiplexing to an output the LCD driver voltage from a plurality of voltages associated with the plurality of LCD driver voltages; and

generating a contrast control signal to select the voltage to output as the LCD drive voltage.

15. The method of claim 11, wherein the step of generating the oscillator control signal further comprises the steps of:

generating the output at a second logical level when the LCD driver voltage falls below the reference voltage by a second predetermined level;

using the latch to latch the output at either the second logical level; and

generating the oscillator control signal to enable the oscillator responsive to the output at the second logical level.

16. The method of claim 11 further comprising the step of disabling the LCD display responsive to an enable control signal.

17. The method of claim 11 further including the step of generating the reference voltage using a bandgap generator.

18. The method of claim 11 further comprising the step of enabling/disabling the LCD display responsive to an enable control signal.