Device and method for detecting a short-circuit during a start-up routine

• US 9,058,766 B2
• Filed: 10/11/2012
• Issued: 06/16/2015
• Est. Priority Date: 10/14/2011
• Status: Active Grant

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Zhang, HaiBo, Li, Jin
• Primary Examiner(s): Crawford, Jason M
• Assistant Examiner(s): Correa, Nelson
• Application Number:
  US13/649,821
• Publication Number:
  US 20130093326A1
• Time in Patent Office: 978 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 2330/10 Dealing with defective pixels
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Abstract

A device and method for detecting a short circuit in an electrical component during a start-up routine. In an embodiment, a device may have a problematic display having a short circuit that may result in damage to other components of the device if the device were allowed to fully startup during a normal start-up routine. Thus, power supplied to the panel may be initiated in stages so as to monitor any current that may be flowing through the panel, which in turn, may be indicative of a short circuit in the panel. If enough “leakage” current is detected through the panel during this staged startup routine, then a short-circuit detection circuit may interrupt the startup routine and lock out the operation of the device until the detected short circuit in the panel can be addressed.

Claims

1. A device comprising:

a display having a first power node and a second power node;

a power supply circuit having first and second supply nodes respectively coupled to the first and second power nodes and configured to generate a first ramped voltage signal on the first supply node during a first phase of a startup routine and generate a second ramped voltage signal on the second supply node during a second phase of the startup routine; and

a detection circuit and a control unit cooperating therewith to

sense a current through the display during the first phase,

responsive to sensing the current, disable the generation of the first ramped voltage signal by the power supply circuit, and

responsive to not detecting the current through the display, disable the detection circuit.

2. The device of claim 1, wherein the display further comprises an active matrix organic light emitting diode display.

3. The device of claim 1, wherein the power supply circuit comprises:

a boost converter including a plurality of switches configured to generate a first output voltage derived from an input voltage; and

an inverting converter including a plurality of switches configured to generate a second output voltage having an opposite polarity as the first output voltage and derived from the input voltage.

4. The device of claim 1, wherein the detection circuit further comprises:

a switch configured to couple an output node of the power supply circuit to a reference node;

a comparator configured to compare a voltage on the output node of the power supply circuit to a reference voltage; and

an interruption circuit configured to interrupt the power supply circuit if the voltage on the output node exceeds the reference voltage.

5. The device of claim 1, further comprising a battery coupled to the power supply circuit.

6. The device of claim 1, further comprising a processor coupled to the power supply circuit and coupled to the display, the processor configured to control the power supply circuit and to control the display.

7. An integrated circuit comprising:

a power supply circuit having first and second supply nodes to be respectively coupled with first and second power nodes of an electronic component, the power supply circuit being configured to generate a first ramped voltage signal on the first supply node during a first phase of a startup routine and generate a second ramped voltage signal on the second supply node during a second phase of the startup routine; and

a detection circuit and a control unit cooperating therewith to

sense a current through the electronic component during the first phase,

responsive to sensing the current, disable the generation of the first ramped voltage signal by the power supply circuit, and

responsive to not detecting the current through the electronic component, disable the detection circuit.

8. The integrated circuit of claim 7 wherein the power supply circuit further comprises a dual DC-DC converter configured to receive an input voltage of approximately 4.6 volts and to produce a voltage of approximately 7.0 volts on the first node after the first phase and to produce a voltage of approximately −

7.0 volts on the second node after the second phase.

9. The integrated circuit of claim 7 wherein threshold voltage comprises a voltage of approximately 300 mV.

10. The integrated circuit of claim 7 further comprising a switch operable to decouple the detection circuit from the second node after the first phase.

11. The integrated circuit of claim 7 wherein said power supply circuit comprises a dual DC-DC voltage converter.

12. A method for a power startup routine, comprising:

enabling a power supply circuit having first and second supply nodes coupled to an electrical component;

generating a first ramped voltage signal on the first supply node during a first phase of the startup routine;

enabling a detection circuit configured to sense a current through the electrical component during the first phase;

in response to detecting the current, disabling the generation of the first ramped voltage signal; and

in response to not detecting a current;

disabling the detection circuit; and

generating a second ramped voltage signal on the second supply node during a second phase of the startup routine.

13. The method of claim 12, wherein the generating the first ramped voltage signal further comprises generating the first ramped voltage signal with a slope dependent upon a first capacitor coupled to the first supply node and the generating the second ramped voltage signal further comprises generating the second ramped voltage signal with a slope dependent upon a second capacitor coupled to the first supply node.

14. The method of claim 13, wherein the size of the second capacitor is related to a short circuit resistance of the electrical component.

15. The method of claim 12, further comprising locking in the disabling of the first ramped voltage signal such that startup routine may not be started again until unlocked.