Integrated circuit having improved radiation immunity

• US 9,058,853 B2
• Filed: 08/16/2012
• Issued: 06/16/2015
• Est. Priority Date: 08/16/2012
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Hart, Michael J., Karp, James
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): BRADLEY, STEPHEN M
• Application Number:
  US13/587,823
• Publication Number:
  US 20140048887A1
• Time in Patent Office: 1,034 Days
• Field of Search: 257/369, 257/372, 257/393, 438/199, 365/156
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; an n-well formed on the substrate; a p-well formed on the substrate; and a p-tap formed in the p-well adjacent to the n-well, wherein the p-tap extends between circuit elements formed in the n-well and circuit elements formed in the p-well, and is coupled to a ground potential. A method of forming an integrated circuit having improved radiation immunity is also described.

Claims

1. An integrated circuit having improved radiation immunity, the integrated circuit comprising:

a substrate;

an n-well formed on the substrate;

a p-well formed on the substrate and extending along the n-well, wherein the integrated circuit comprises a plurality of memory cells having n-channel transistors in the p-well and p-channel transistors in the n-well and extending in a column along the p-well and n-well; and

a p-tap formed in the p-well adjacent to the n-well, wherein the p-tap extends along the column of memory cells between the p-channel transistors formed in the n-well and the n-channel transistors formed in the p-well and is coupled to a ground potential.

2. The integrated circuit of claim 1, further comprising a second p-well adjacent to the n-well on another side of the n-well.

3. The integrated circuit of claim 2, wherein the second p-well comprises a second p-tap which is coupled to ground.

4. The integrated circuit of claim 3, wherein the second p-well comprises transistor elements, and the p-tap is between the n-well and the transistor elements formed in the second p-well.

5. The integrated circuit of claim 4, wherein the transistor elements of the second p-well are in a column.

6. The integrated circuit of claim 1, wherein the p-tap surrounds the n-well.

7. A method of forming integrated circuit having improved radiation immunity, the method comprising:

forming an n-well on substrate;

forming a p-well on the substrate and extending along the n-well, wherein the integrated circuit comprises a plurality of memory cells having n-channel transistors in the p-well and p-channel transistors in the n-well and extending in a column along the p-well and the n-well; and

forming a p-tap in the p-well adjacent to the n-well, wherein the p-tap extends along the column of the memory cells between the p-channel transistors formed in the n-well and the n-channel transistors formed in the p-well and is coupled to a ground potential.

8. The method of claim 7, further comprising forming a second p-well adjacent to the n-well on another side of the n-well.

9. The method of claim 8, further comprising forming a second p-tap in the second p-well, wherein the second p-tap is coupled to ground.

10. The method of claim 7, wherein the n-channel transistors are formed in a first column and the p-channel transistors are formed in a second column.

11. The method of claim 10, wherein forming the p-tap comprises forming the p-tap between the n-channel transistors and the p-channel transistors of the plurality of memory cells.

12. The method of claim 7, wherein forming a p-tap comprises forming the p-tap around the n-well.