Power management SRAM write bit line drive circuit
First Claim
1. A static random access memory (SRAM) comprising:
- two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC);
a write driver logic coupled to the WBL and the WBLC, the write driver logic adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel;
the write driver logic further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, wherein the downlevel is a voltage suitable to be interpreted as a downlevel on the WBLC by two or more SRAM cells.
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Abstract
A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, where the downlevel is a second supply voltage lower than the first supply voltage.
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Citations
20 Claims
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1. A static random access memory (SRAM) comprising:
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two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC); a write driver logic coupled to the WBL and the WBLC, the write driver logic adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel; the write driver logic further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, wherein the downlevel is a voltage suitable to be interpreted as a downlevel on the WBLC by two or more SRAM cells. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A static random access memory (SRAM) comprising:
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two or more SRAM memory cells connected with a write bit line (WBL); a write driver logic coupled to the WBL; the write driver logic adapted to drive the WBL to a voltage uplevel below a first supply voltage in response to a first logical value on a data input; the write driver logic further adapted to shut off the drive to the WBL when the WBL reaches the uplevel; the write driver logic further adapted to drive the WBL to a downlevel, in response to a second logical value on the data input, wherein the downlevel is a voltage suitable to be interpreted as a downlevel on the WBLC by two or more SRAM cells. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A design structure tangibly embodied in a machine-readable storage medium used in a design process of an SRAM, the design structure having elements that, when processed in a semiconductor manufacturing facility, produce an SRAM that comprises:
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two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC); a write driver logic coupled to the WBL and the WBLC, the write driver logic adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel; the write driver logic further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, wherein the downlevel is a second supply voltage lower than the first supply voltage. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification