Pulse output circuit, display device, and electronic device
First Claim
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1. A pulse output circuit comprising:
- a first transistor, one of a source and a drain of the first transistor being electrically connected to a first wiring to which a first clock signal is supplied;
a second transistor, one of a source and a drain of the second transistor being electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the second transistor being electrically connected to a second wiring to which a first potential is supplied;
a third transistor, a gate of the third transistor being electrically connected to a third wiring to which a second clock signal is supplied, one of a source and a drain of the third transistor being electrically connected to a gate of the first transistor, and the other of the source and the drain of the third transistor being electrically connected to a fourth wiring to which a second potential is supplied;
a fourth transistor, a gate of the fourth transistor being electrically connected to a fifth wiring to which a third clock signal is supplied, and one of a source and a drain of the fourth transistor being electrically connected to the gate of the first transistor; and
a fifth transistor, a gate of the fifth transistor being electrically connected to a sixth wiring to which a reset signal is supplied, one of a source and a drain of the fifth transistor being electrically connected to the gate of the second transistor, and the other of the source and the drain of the fifth transistor being electrically connected to a seventh wiring to which a third potential is supplied,wherein a potential of the gate of the first transistor is configured to be changed by the third transistor and the fourth transistor in accordance with the second clock signal and the third clock signal in a period during the pulse output circuit outputs a low-level signal.
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Abstract
An object is to suppress the stress applied to a transistor as well as suppressing generation of defective operation. In a pulse output circuit having a function of outputting a pulse signal and including a transistor that controls whether to set the pulse signal to high level, in a period during which the pulse signal output from the pulse output circuit is at low level, the potential of a gate of a transistor is not set to a constant value but intermittently set to a value higher than the potential VSS. Accordingly, the stress to the transistor can be suppressed.
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Citations
20 Claims
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1. A pulse output circuit comprising:
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a first transistor, one of a source and a drain of the first transistor being electrically connected to a first wiring to which a first clock signal is supplied; a second transistor, one of a source and a drain of the second transistor being electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the second transistor being electrically connected to a second wiring to which a first potential is supplied; a third transistor, a gate of the third transistor being electrically connected to a third wiring to which a second clock signal is supplied, one of a source and a drain of the third transistor being electrically connected to a gate of the first transistor, and the other of the source and the drain of the third transistor being electrically connected to a fourth wiring to which a second potential is supplied; a fourth transistor, a gate of the fourth transistor being electrically connected to a fifth wiring to which a third clock signal is supplied, and one of a source and a drain of the fourth transistor being electrically connected to the gate of the first transistor; and a fifth transistor, a gate of the fifth transistor being electrically connected to a sixth wiring to which a reset signal is supplied, one of a source and a drain of the fifth transistor being electrically connected to the gate of the second transistor, and the other of the source and the drain of the fifth transistor being electrically connected to a seventh wiring to which a third potential is supplied, wherein a potential of the gate of the first transistor is configured to be changed by the third transistor and the fourth transistor in accordance with the second clock signal and the third clock signal in a period during the pulse output circuit outputs a low-level signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A pulse output circuit comprising:
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a first transistor, one of a source and a drain of the first transistor being electrically connected to a first wiring to which a first clock signal is supplied; a second transistor, one of a source and a drain of the second transistor being electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the second transistor being electrically connected to a second wiring to which a first potential is supplied; a third transistor, a gate of the third transistor being electrically connected to a third wiring to which a second clock signal is supplied, one of a source and a drain of the third transistor being electrically connected to a gate of the first transistor, and the other of the source and the drain of the third transistor being electrically connected to a fourth wiring to which a second potential is supplied; a fourth transistor, a gate of the fourth transistor being electrically connected to a fifth wiring to which a third clock signal is supplied, and one of a source and a drain of the fourth transistor being electrically connected to the gate of the first transistor; and a fifth transistor, a gate of the fifth transistor being electrically connected to a sixth wiring to which a reset signal is supplied, one of a source and a drain of the fifth transistor being electrically connected to the gate of the second transistor, and the other of the source and the drain of the fifth transistor being electrically connected to a seventh wiring to which a third potential is supplied, wherein a potential of the gate of the first transistor is configured to be set to the second potential by turning on the third transistor and turning off the fourth transistor in accordance with the second clock signal and the third clock signal in a period during the pulse output circuit outputs a low-level signal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A pulse output circuit comprising:
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a first transistor, one of a source and a drain of the first transistor being electrically connected to a first wiring to which a first clock signal is supplied; a second transistor, one of a source and a drain of the second transistor being electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain of the second transistor being electrically connected to a second wiring to which a first potential is supplied; a third transistor, a gate of the third transistor being electrically connected to a third wiring to which a second clock signal is supplied, one of a source and a drain of the third transistor being electrically connected to a gate of the first transistor, and the other of the source and the drain of the third transistor being electrically connected to a fourth wiring to which a second potential is supplied; a fourth transistor, a gate of the fourth transistor being electrically connected to a fifth wiring to which a third clock signal is supplied, and one of a source and a drain of the fourth transistor being electrically connected to the gate of the first transistor; and a fifth transistor, a gate of the fifth transistor being electrically connected to a sixth wiring to which a reset signal is supplied, one of a source and a drain of the fifth transistor being electrically connected to the gate of the second transistor, and the other of the source and the drain of the fifth transistor being electrically connected to a seventh wiring to which a third potential is supplied. - View Dependent Claims (18, 19, 20)
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Specification