Semiconductor device

• US 9,059,009 B2
• Filed: 12/25/2012
• Issued: 06/16/2015
• Est. Priority Date: 02/09/2012
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Horio, Masafumi, Fukuda, Kyohei, Hori, Motohito, Ikeda, Yoshinari
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US14/368,432
• Publication Number:
  US 20140346676A1
• Time in Patent Office: 903 Days
• Field of Search: 257/698, 257/692, 257/678, 257/723, 257/E23.079
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48139 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4912 Layout
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49844 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/01 Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

Semiconductor chips are disposed on an insulating substrate with conductive patterns, and a printed circuit board with metal pins is disposed above the insulating substrate with conductive patterns, with the semiconductor chips therebetween. A plurality of external lead terminals is fixed to the insulating substrate with conductive patterns, with the plurality of external lead terminals disposed adjacent to each other in parallel. Furthermore, metal foil pieces formed on front and rear surfaces of the printed circuit board with metal pins respectively so as to face each other, are disposed above the semiconductor chips.

Claims

1. A semiconductor device, comprising:

an insulating substrate with conductive patterns, having at least a first conductive pattern, a second conductive pattern, and a third conductive pattern, on a first insulating substrate;

a positive-electrode external lead terminal fixed to the first conductive pattern;

a negative-electrode external lead terminal fixed to the second conductive pattern;

an external lead terminal of intermediate potential fixed to the third conductive pattern;

a first semiconductor element having one surface fixed to the first conductive pattern;

a second semiconductor element having one surface fixed to the third conductive pattern; and

an insulating substrate with conductive pins, having conductive layers on front and rear surfaces of a second insulating substrate respectively, a plurality of first conductive pins fixed to the conductive layer on the rear surface of the second insulating substrate, and a plurality of second conductive pins fixed to the conductive layer on the front surface of the second insulating substrate,

wherein the positive-electrode external lead terminal and the negative-electrode external lead terminal are disposed adjacent to each other in parallel,

a portion of the pins constituting the plurality of first conductive pins is fixed to the other surface of the first semiconductor element, and another portion of pins constituting the plurality of first conductive pins are fixed to the third conductive pattern,

a portion of the pins constituting the plurality of second conductive pins is fixed to the other surface of the second semiconductor element, and another portion of the pins constituting the plurality of second conductive pins are fixed to the second conductive pattern,

the insulating substrate with conductive pins is disposed on the other surface of the first semiconductor element and the other surface of the second semiconductor element, and

an area in which the first semiconductor element and the second semiconductor element are disposed has a size substantially equivalent to a face of the insulating substrate with conductive pins.

3. The semiconductor device according to claim 1, wherein the insulating substrate with conductive pins is a printed circuit board with metal pins comprising:

metal foil pieces fixed respectively to the front and rear surfaces of the second insulating substrate made of ceramic,

a first metal pin fixed to the metal foil piece on the rear surface, and

a second metal pin fixed to the metal foil piece on the front surface.

4. The semiconductor device according to claim 1, wherein the positive-electrode external lead terminal and the negative-electrode external lead terminal are rectangular conductive plates.

5. The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element are connected in series through the first conductive pins and the third conductive pattern and are 2-in-1, 4-in-1, or 6-in-1 semiconductor modules each configuring an upper arm or a lower arm.

6. The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element each includes a switching transistor chip and a diode chip connected antiparallel to the switching transistor chip.

7. The semiconductor device according to claim 6, wherein the switching transistor chip is an IGBT chip, a MOSFET chip, a junction field-effect transistor chip, or a bipolar transistor chip, and the diode chip is a pn diode chip or a Schottky barrier diode chip.

8. The semiconductor device according to claim 1, wherein three sides of the second conductive pattern are surrounded by the first conductive pattern.

9. The semiconductor device according to claim 1, wherein the plurality of second conductive pins fixed to the second conductive pattern penetrate the second insulating substrate.

2. A semiconductor device, comprising:

a first insulating substrate with conductive patterns having at least a first conductive pattern and a second conductive pattern, on a first insulating substrate;

a second insulating substrate with conductive patterns having at least a third conductive pattern on a third insulating substrate;

a positive-electrode external lead terminal fixed to the first conductive pattern;

a negative-electrode external lead terminal fixed to the second conductive pattern;

an external lead terminal of intermediate potential fixed to the third conductive pattern;

a first semiconductor element having one surface fixed to the first conductive pattern;

a second semiconductor element having one surface fixed to the third conductive pattern; and

an insulating substrate with conductive pins, having conductive layers on front and rear surfaces of a second insulating substrate respectively, a plurality of first conductive pins fixed to the conductive layer on the rear surface of the second insulating substrate, and a plurality of second conductive pins fixed to the conductive layer on the front surface of the second insulating substrate,

wherein the positive-electrode external lead terminal and the negative-electrode external lead terminal are disposed adjacent to each other in parallel,

a portion of pins constituting the plurality of first conductive pins is fixed to the other surface of the first semiconductor element, and another portion of pins constituting the plurality of first conductive pins are fixed to the third conductive pattern,

a portion of pins constituting the plurality of second conductive pins is fixed to another portion of surface of the second semiconductor element, and the other pins constituting the plurality of second conductive pins are fixed to the second conductive pattern, and

the insulating substrate with conductive pins is sandwiched between the other surface of the first semiconductor element and the other surface of the second semiconductor element.

10. The semiconductor device according to claim 2, wherein the insulating substrate with conductive pins is a printed circuit board with metal pins comprising:

metal foil pieces fixed respectively to the front and rear surfaces of the second insulating substrate made of ceramic,

a first metal pin fixed to the metal foil piece on the rear surface, and

a second metal pin fixed to the metal foil piece on the front surface.

11. The semiconductor device according to claim 2, wherein the positive-electrode external lead terminal and the negative-electrode external lead terminal are rectangular conductive plates.

12. The semiconductor device according to claim 2, wherein the first semiconductor element and the second semiconductor element are connected in series through the first conductive pins and the third conductive pattern and are 2-in-1, 4-in-1, or 6-in-1 semiconductor modules each configuring an upper arm or a lower arm.

13. The semiconductor device according to claim 2, wherein the first semiconductor element and the second semiconductor element each includes a switching transistor chip and a diode chip connected antiparallel to the switching transistor chip.

14. The semiconductor device according to claim 13, wherein the switching transistor chip is an IGBT chip, a MOSFET chip, a junction field-effect transistor chip, or a bipolar transistor chip, and the diode chip is a pn diode chip or a Schottky barrier diode chip.

15. The semiconductor device according to claim 2, wherein three sides of the second conductive pattern are surrounded by the first conductive pattern.

16. The semiconductor device according to claim 2, wherein the second conductive pins fixed to the second conductive pattern penetrate the second insulating substrate.