3-D inductor and transformer

• US 9,059,026 B2
• Filed: 06/24/2013
• Issued: 06/16/2015
• Est. Priority Date: 06/01/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yen, Hsiao-Tsung, Kuo, Chin-Wei, Hu, Hsien-Pin, Liu, Sally, Chen, Ming-Fa, Lu, Jhe-Ching
• Primary Examiner(s): REAMES, MATTHEW L
• Application Number:
  US13/925,558
• Publication Number:
  US 20140374875A1
• Time in Patent Office: 722 Days
• US Class Current: 1/1
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.

Claims

1. A semiconductor device comprising:

an first integrated circuit die;

an interposer comprising;

a first metallization layer on a first side of the interposer, the first metallization layer comprising a first spiral pattern and a second spiral pattern, the second spiral pattern being distinct from the first spiral pattern, the first spiral pattern having a first portion extending along an inner side of an entire circumference of the second spiral pattern; and

a second metallization layer on the first metallization layer;

a third metallization layer on a second side of the interposer, the second side being opposite the first side, the third metallization layer comprising a third spiral pattern and a fourth spiral pattern, the fourth spiral pattern being distinct from the third spiral pattern; and

a fourth metallization layer on the third metallization layer; and

a first set of conductive bumps on a first side of the interposer and bonding the first integrated circuit die to the interposer, at least one of the first set of conductive bumps being coupled to at least one of the first spiral pattern the second spiral pattern.

2. The semiconductor device of claim 1 further comprising:

a substrate; and

a second set of conductive bumps on a second side of the interposer and bonding the interposer to the substrate, the second side being opposite the first side.

3. The semiconductor device of claim 2 further comprising:

a second integrated circuit die; and

a third set of conductive bumps on the second side of the interposer and bonding the second integrated circuit die to the interposer, at least one of the third set of conductive bumps being coupled to at least one of the third spiral pattern the fourth spiral pattern.

4. The semiconductor device of claim 1, wherein the interposer further comprises

a substrate, the first metallization layer being on a first side of the substrate, the third metallization layer being on a second side of the substrate;

and

a through substrate via extending through the substrate, the through substrate via being electrically coupled to the first and second metallization layers.

5. The semiconductor device of claim 1, wherein the integrated circuit die further comprises a first dielectric layer, the first metallization layer being in the first dielectric layer, and wherein the interposer further comprises a second dielectric layer, the second metallization layer being in the second dielectric layer.

18. The semiconductor device of claim 1, wherein the second metallization layer comprises a first cross link and a second cross link, and the fourth metallization layer comprises a third cross link and a fourth cross link.

19. The semiconductor device of claim 18, wherein the first cross link electrically couples the first portion of the first spiral pattern to a second portion of the first spiral pattern, and the second cross link electrically couples a first portion of the second spiral pattern to a second portion of the second spiral pattern.

20. The semiconductor device of claim 1, wherein the first spiral pattern further comprises a second portion and a third portion, the second portion extending along an outer side of a first half circumference of the second spiral pattern, and the third portion extending along an outer side of a second half circumference of the second spiral pattern, the first half circumference and the second half circumference forming the entire circumference of the second spiral pattern.

6. An interposer comprising:

a first set of trace links on a first side of a substrate, the first set of trace links forming a first conductive pattern;

a second set of trace links over the first set of trace links, the second set of trace links forming a second conductive pattern;

a third set of trace links on a second side of the substrate, the second side being opposite the first side, the third set of trace links forming a third conductive pattern;

a fourth set of trace links over the third set of trace links, the fourth set of trace links forming a fourth conductive pattern; and

a plurality of through substrate vias (TSVs) extending through the substrate, each of the plurality of TSVs having a same height, at least one of the plurality of TSVs electrically coupling the first conductive pattern and the third conductive pattern to form a first coil, at least one other of the plurality of TSVs electrically coupling the second conductive pattern and the fourth conductive pattern to form a second coil, the first coil being distinct from the second coil, each of the plurality of TSVs having a first end and a second end, the first ends being coplanar with a first side of the substrate and the second ends being coplanar with the second side of the substrate, the first and second sides being major surfaces of the substrate.

7. The interposer of claim 6, wherein the first coil is an inner coil surrounded by the second coil.

8. The interposer of claim 6, wherein each of the first and third sets of trace links has at least a portion with a first longitudinal axis and at least a second portion with a second longitudinal axis, the second longitudinal axis being different than the first longitudinal axis.

9. The interposer of claim 6, wherein each of the second and fourth sets of trace links has only a single longitudinal axis.

10. The interposer of claim 6 further comprising:

a first conductive pad on the first side of the substrate, the first conductive pad directly contacting a first end of the at least one of the plurality of TSVs;

a first via coupling the first conductive pad and at least one of the second set of trace links;

a second conductive pad on the second side of the substrate, the second conductive pad directly contacting a second end of the at least one of the plurality of TSVs; and

a second via coupling the second conductive pad and at least one of the fourth set of trace links.

11. An interposer comprising:

a first metallization layer on a first side of a semiconductor substrate, the first metallization layer comprising a first spiral pattern and a second spiral pattern, the second spiral pattern being distinct from the first spiral pattern, a first part of the first spiral pattern surrounding the second spiral pattern, and the second spiral pattern surrounding a second part of the first spiral pattern;

a second metallization layer on the first metallization layer, the second metallization layer comprising a first cross link and a second cross link;

a third metallization layer on a second side of the semiconductor substrate, the second side being opposite the first side, the third metallization layer comprising a third spiral pattern and a fourth spiral pattern, the fourth spiral pattern being distinct from the third spiral pattern;

a fourth metallization layer on the third metallization layer, the fourth metallization layer comprising a third cross link and a fourth cross link; and

through substrate vias (TSVs) extending through the semiconductor substrate, the through substrate vias electrically coupling the first metallization layer to the third metallization layer.

12. The interposer of claim 11, wherein the first cross link electrically couples a first portion of the first spiral pattern to a second portion of the first spiral pattern, and the second cross link electrically couples a first portion of the second spiral pattern to a second portion of the second spiral pattern.

13. The interposer of claim 12, wherein the first cross link further comprises:

a metal line in the second metallization layer;

a first via electrically coupling the first portion of the first spiral pattern to the metal line; and

a second via electrically coupling the second portion of the first spiral pattern to the metal line.

14. The interposer of claim 11, wherein a first part of the third spiral pattern surrounds the fourth spiral pattern, and the fourth spiral pattern surrounds a second part of the third spiral pattern.

15. The interposer of claim 11, wherein at least one TSV electrically couples the first spiral pattern to the third spiral pattern, and at least one other TSV electrically couples the second spiral pattern to the fourth spiral pattern.

16. The interposer of claim 11, wherein the semiconductor substrate comprises silicon.

17. The interposer of claim 11, wherein each of the TSVs have a first end and a second end, the first ends being coplanar with a first side of the semiconductor substrate and the second ends being coplanar with the second side of the semiconductor substrate, the first and second sides being major surfaces of the semiconductor substrate.