Semiconductor device

• US 9,059,083 B2
• Filed: 09/14/2007
• Issued: 06/16/2015
• Est. Priority Date: 09/14/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Ewe, Henrik, Mahler, Joachim, Mengel, Manfred, Engl, Reimund, Hoeglauer, Josef, Dangelmaier, Jochen
• Primary Examiner(s): Lee, Eugene
• Assistant Examiner(s): Jiang, Fang-Xing
• Application Number:
  US11/855,712
• Publication Number:
  US 20090072379A1
• Time in Patent Office: 2,832 Days
• Field of Search: 257675-728, 257/E21.418, 257/E21.499, 257/E29.257, 438/259
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02288 printing, e.g. ink-jet printing per se B41J
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 21/4821 Flat leads, e.g. lead frames with or without insulating supports
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/24011 Deposited, e.g. MCM-D type
• CPC Class Codes: H01L 2224/2402 Laminated, e.g. MCM-L type
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24246 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24998 Reinforcing structures, e.g. ramp-like support
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/76155 : Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 2224/82101 : by additive methods, e.g. direct writing
• CPC Class Codes: H01L 2224/82102 : using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/82103 : using laser direct writing
• CPC Class Codes: H01L 2224/82951 : Forming additional members
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/49524 : the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49534 : Multi-layer
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H05K 3/4661 : Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor other insulating materials H05K3/387

Abstract

A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.

Claims

1. A semiconductor device comprising:

a carrier;

a semiconductor chip having side faces extending between a top surface and a bottom surface, the bottom surface attached to the carrier;

a structured insulating layer disposed directly on the side faces, the top surface, and a surface of the carrier leaving contacts on the top surface of the semiconductor chip and contact pads on the carrier exposed;

a first conducting line having a first thickness;

a second conducting line having a second thickness;

wherein the first thickness is smaller than the second thickness, and wherein the first and second conducting lines are disposed on the structured insulating layer and extend between contacts on the top surface of the semiconductor chip and contact pads on the carrier;

a housing of the semiconductor device comprising a mold material encapsulating the semiconductor chip, the structured insulating layer, and the first and second conducting lines; and

an insulating barrier covering the first conducting line, exposing the second conducting line and being encapsulated by the mold material of the housing.

2. The semiconductor device of claim 1, further comprising:

a third conducting line deposited over the insulating barrier.

3. The semiconductor device of claim 1, comprising wherein the carrier is of a TSLP type.

4. The semiconductor device of claim 1, comprising wherein the carrier is made of an insulating material.

5. The semiconductor device of claim 1, further comprising:

a mold material encapsulating the semiconductor chip and the first and second conducting lines.

6. The semiconductor device of claim 1, wherein the first deposited conducting line and the second deposited conducting line are plated metal layers.

7. The semiconductor device of claim 1, wherein the second conducting line is composed of a base part having substantially the first thickness and a reinforcement part disposed on the based part to obtain the second thickness.

8. The semiconductor device of claim 7, wherein the first conducting line and the base part of the second conducting line are made of sintered metal particles.

9. The semiconductor device of claim 8, wherein the reinforcement part of the second conducting line is made of a galvanically deposited metal.

10. A semiconductor device comprising:

a carrier made of metal;

a semiconductor chip having side faces extending between a top surface and a bottom surface, the bottom surface attached to the carrier;

a structured insulating layer disposed directly on the side faces, the top surface, and a surface of the carrier leaving contacts on the top surface of the semiconductor chip and contact pads on the carrier exposed;

a first conducting line disposed directly on the structured insulating layer and extending between a contact on the top surface of the semiconductor chip and a contact pad on the carrier, the first conducting line being disposed directly on at least one contact on the surface of the semiconductor chip and directly on surfaces of the semiconductor chip other than the at least one contact;

an insulating layer applied over the first deposited conducting line;

a second conducting line deposited over the insulating layer; and

a housing of the semiconductor device comprising a mold material encapsulating the semiconductor chip, the structured insulating layer, the first and second conducting lines, and the insulating layer, wherein a thickness of the second conducting line is greater than a thickness of the first conducting line.