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Buried gate transistor

  • US 9,059,141 B2
  • Filed: 10/31/2012
  • Issued: 06/16/2015
  • Est. Priority Date: 07/06/2005
  • Status: Expired due to Fees
First Claim
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1. A method of making a semiconductor device, the method comprising:

  • providing a semiconductor body with a first active region, a second active region, and an isolation region between the first active region and the second active region;

    forming a recess in a surface of the semiconductor body, the recess extending across the first active region, the isolation region and the second active region, the recess having a first depth from a top surface of the semiconductor body;

    forming a gate dielectric within the recess;

    forming doped channel regions in a bottom surface of the recess in the first and second active regions;

    forming a hard mask over the semiconductor body;

    implanting halo dopants to form halo regions along entire sidewalls of the recess after forming the doped channel regions in the first and second active regions, wherein, during the implanting, the hard mask shadows the halo dopants from reaching the bottom surface of the recess and a top surface of the semiconductor body adjacent the recess;

    forming a gate electrode in the recess;

    forming sidewall spacers adjacent the gate electrode; and

    after forming the sidewall spacers, forming first and second source/drain regions in the first active region and third and fourth source/drain regions in the second active region, the first source/drain region being spaced from the second source/drain region by the gate electrode and third source/drain region being spaced from the fourth source/drain region by the gate electrode, wherein the halo regions extend deeper than the first and second source/drain regions, wherein after forming the first and second source/drain regions, portions of the doped channel regions form a non-planar current channel for a transistor, wherein the non-planar current channel comprises a first portion along a side wall of the gate electrode, a second portion at a bottom surface of the gate electrode, and a third portion along an opposite sidewall of the gate electrode, wherein the halo regions intersect with the non-planar current channel.

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