Buried gate transistor

• US 9,059,141 B2
• Filed: 10/31/2012
• Issued: 06/16/2015
• Est. Priority Date: 07/06/2005
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Lindsay, Richard, Hierlemann, Matthias
• Primary Examiner(s): HUBER, ROBERT T
• Application Number:
  US13/665,448
• Publication Number:
  US 20130059424A1
• Time in Patent Office: 958 Days
• Field of Search: 257330-334, 257/E29.26, 257/E21.384, 257/E21.419, 257/E21.428, 257/E21.433, 257/E21.429, 438/199, 438/259, 438/270
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 : with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.

Claims

1. A method of making a semiconductor device, the method comprising:

providing a semiconductor body with a first active region, a second active region, and an isolation region between the first active region and the second active region;

forming a recess in a surface of the semiconductor body, the recess extending across the first active region, the isolation region and the second active region, the recess having a first depth from a top surface of the semiconductor body;

forming a gate dielectric within the recess;

forming doped channel regions in a bottom surface of the recess in the first and second active regions;

forming a hard mask over the semiconductor body;

implanting halo dopants to form halo regions along entire sidewalls of the recess after forming the doped channel regions in the first and second active regions, wherein, during the implanting, the hard mask shadows the halo dopants from reaching the bottom surface of the recess and a top surface of the semiconductor body adjacent the recess;

forming a gate electrode in the recess;

forming sidewall spacers adjacent the gate electrode; and

after forming the sidewall spacers, forming first and second source/drain regions in the first active region and third and fourth source/drain regions in the second active region, the first source/drain region being spaced from the second source/drain region by the gate electrode and third source/drain region being spaced from the fourth source/drain region by the gate electrode, wherein the halo regions extend deeper than the first and second source/drain regions, wherein after forming the first and second source/drain regions, portions of the doped channel regions form a non-planar current channel for a transistor, wherein the non-planar current channel comprises a first portion along a side wall of the gate electrode, a second portion at a bottom surface of the gate electrode, and a third portion along an opposite sidewall of the gate electrode, wherein the halo regions intersect with the non-planar current channel.

2. The method of claim 1, wherein the first active region comprises an n-doped semiconductor and the second active region comprises a p-doped semiconductor.

3. The method of claim 1, further comprising:

electrically coupling the first source/drain region to the third source/drain region;

electrically coupling the second source/drain region to a first supply voltage node; and

electrically coupling the fourth source/drain region to a second supply voltage node.

4. A method of making a buried gate, the method comprising:

forming a recess in a surface of a semiconductor body, the recess having a first depth from a top surface of the semiconductor body;

forming a high-k dielectric liner in the recess;

forming a doped channel in a bottom surface of the recess;

forming halo regions along sidewalls of the recess after forming the doped channel, wherein forming the halo regions along sidewalls of the recess comprises forming a hard mask over the semiconductor body, and implanting a halo implant along entire sidewalls of the recess, wherein the hard mask shadows the halo implant to reach the bottom surface of the recess and a top surface of the semiconductor body adjacent the recess;

forming a gate electrode in the recess;

forming sidewall spacers adjacent the gate electrode; and

after forming the sidewall spacers, forming first and second highly doped source/drain regions in the semiconductor body, the first and second highly doped source/drain regions being laterally spaced by the gate electrode, wherein the halo regions extend deeper than the first and second highly doped source/drain regions, wherein after forming the first and second source/drain regions, portions of the doped channel form a non-planar current channel for a buried gate transistor, wherein the non-planar current channel comprises a first portion along a side wall of the gate electrode, a second portion at a bottom surface of the gate electrode, and a third portion along an opposite sidewall of the gate electrode, wherein the halo regions intersect with the non-planar current channel.

5. The method of claim 4, further comprising

depositing an epitaxial semiconductor layer before forming the first and second highly doped source/drain regions;

and

siliciding the epitaxial semiconductor layer.

6. The method of claim 4, wherein the high-k dielectric liner is conformal along the bottom surface and along the sidewalls of the recess.

7. The method of claim 4, further comprising forming sidewalls spacers on a portion of the sidewalls of the gate electrode before forming the first and second highly doped source/drain regions.

8. A method of making a buried gate, the method comprising:

forming a recess in a surface of a semiconductor body, the recess having a first depth from a top surface of the semiconductor body;

forming a dielectric liner in the recess;

forming a doped channel in a bottom surface of the recess;

forming halo regions along sidewalls of the recess after forming the doped channel, wherein forming the halo regions along sidewalls of the recess comprises forming a hard mask over the semiconductor body, and implanting a halo implant along entire sidewalls of the recess, wherein the hard mask shadows the halo implant to reach the bottom surface of the recess and a top surface of the semiconductor body adjacent the recess;

forming a gate electrode in the recess;

forming sidewall spacers adjacent the gate electrode; and

after forming the sidewall spacers, forming first and second highly doped source/drain regions in the semiconductor body, the first and second highly doped source/drain regions being laterally spaced by the gate electrode, wherein the halo regions extend deeper than the first and second highly doped source/drain regions, wherein after forming the first and second source/drain regions, portions of the doped channel form a non-planar current channel for a buried gate transistor, wherein the non-planar current channel comprises a first portion along a side wall of the gate electrode, a second portion at a bottom surface of the gate electrode, and a third portion along an opposite sidewall of the gate electrode, wherein the halo regions intersect with the non-planar current channel.

9. The method of claim 8, wherein forming the recess comprises lithographically patterning and etching the recess between about 5 nm and about 200 nm.

10. The method of claim 8, wherein forming the dielectric liner comprises thermally growing an oxide layer.

11. The method of claim 8, wherein forming the gate electrode comprises forming a buried gate electrode that extends out of an active region, the method further comprising:

forming sidewall spacers along sidewalls of the gate electrode on the top surface of the semiconductor body; and

forming a silicide over the first and second source/drain regions, the silicide being laterally spaced from the gate electrode by the sidewall spacers.

12. The method of claim 8, where the halo regions are implanted using a tilt angle implant that uses the recess and geometry of the hard mask to shadow, and thereby localize, the implant solely at edges of a channel while avoiding implant in bulk of the channel.

13. The method of claim 8, further comprising forming a first raised source/drain region over the first source/drain region and a second raised source/drain region over the second source/drain region.