Method for producing bonding connection of semiconductor device

• US 9,059,182 B2
• Filed: 09/14/2006
• Issued: 06/16/2015
• Est. Priority Date: 09/14/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Maier, Hubert, Detzel, Thomas
• Primary Examiner(s): Jung, Michael
• Application Number:
  US11/521,087
• Publication Number:
  US 20070063318A1
• Time in Patent Office: 3,197 Days
• Field of Search: 257/784
• US Class Current: 1/1
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48455 Details of wedge bonds
• CPC Class Codes: H01L 2224/48458 of the interface with the bonding area
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/85121 Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/85 using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

An arrangement is employed in a semiconductor device having a semiconductor body, the semiconductor body having a surface. The arrangement includes a surface portion on which a first metallization layer is arranged, and an alignment pattern arranged between the surface portion and the first metallization layer.

Claims

1. A method for producing a bonding connection of a semiconductor device, the method comprising:

providing a semiconductor body, the semiconductor body having a surface, the surface comprising a surface portion on which a first metallization layer is arranged such that a section of the first metallization layer forms a surface of the semiconductor device, and an alignment pattern arranged between the surface portion and the first metallization layer, the alignment pattern causing local elevations in the first metallization layer above the surface portion,

determining a position of the alignment pattern,

determining a bonding position on the first metallization layer in the region of the surface portion on the basis of the determined position of the alignment pattern, and

producing a bonding connection between the bonding partner and the first metallization layer at the bonding position.

2. The method as claimed in claim 1, wherein determining the position of the alignment pattern further comprises determining the position of local elevations of the first metallization layer that are arranged above the alignment pattern.

3. The method as claimed in claim 1, further comprising using an image recognition system to determine the position of the alignment pattern.

4. The method as claimed in claim 1, wherein the alignment pattern is formed of a dielectric material.

5. The method as claimed in claim 1, wherein providing the semiconductor body further comprises providing a second metallization layer arranged between the first metallization layer and the surface portion, and wherein the alignment pattern is formed from a patterned intermetal dielectric arranged between the first metallization layer and the second metallization layer.

6. The method as claimed in claim 1, wherein providing the semiconductor body further comprises providing a second metallization layer arranged between the first metallization layer and the surface portion, and wherein the alignment pattern is arranged between the surface portion and the second metallization layer.

7. The method as claimed in claim 1, wherein the alignment pattern is disposed directly on the surface portion.

8. The method as claimed in claim 1, wherein the alignment pattern is arranged along a line.

9. The method as claimed in claim 1, wherein the alignment pattern is arranged along an outline of a circle or an ellipse.

10. The method as claimed in claim 1, wherein the alignment pattern is arranged along the outline of a polygon.

11. The method as claimed in claim 1, wherein the alignment pattern has at least two spaced-apart pattern features.