Semiconductor device

• US 9,059,238 B2
• Filed: 02/10/2014
• Issued: 06/16/2015
• Est. Priority Date: 09/08/2011
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Momota, Seiji, Abe, Hitoshi, Kurata, Naoko
• Primary Examiner(s): Stark, Jarret
• Assistant Examiner(s): Ahmed, Shahed
• Application Number:
  US14/176,610
• Publication Number:
  US 20140159107A1
• Time in Patent Office: 491 Days
• Field of Search: 257/330, 257/510, 257/520, 257/586
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

Some aspects of the invention include a trench gate structure including a p base layer, an n⁺ emitter region, a trench, a gate oxide film, and a doped polysilicon gate electrode is provided in an active region. A p-type extension region formed by extending the p base layer to an edge termination structure region can be provided in the circumference of a plurality of trenches. One or more annular outer trenches which are formed at the same time as the plurality of trenches are provided in the p-type extension region. The annular outer trenches can surround all of the trenches. A second gap between the annular outer trench and the outermost trench or between adjacent annular outer trenches is less than a first gap between adjacent trenches.

Claims

1. A semiconductor device comprising:

an active region; and

an edge termination structure region that surrounds the active region,

wherein the active region includes;

a first-conduction-type drift layer that is a first-conduction-type semiconductor substrate;

a second-conduction-type base layer that is provided in one main surface of the first-conduction-type semiconductor substrate;

a first-conduction-type semiconductor region that is selectively provided in the second-conduction-type base layer;

a plurality of trenches that extend from the one main surface of the first-conduction-type semiconductor substrate to the first-conduction-type drift layer through the first-conduction-type semiconductor region and the second-conduction-type base layer and are arranged with a predetermined first gap therebetween;

a trench gate structure including a gate insulating film that is provided in the trench along an inner wall of the trench and a gate electrode that is provided in the trench with the gate insulating film interposed therebetween;

a metal electrode that contacts the second-conduction-type base layer and the first-conduction-type semiconductor region;

a second-conduction-type extension region that is a portion of the second-conduction-type base layer which extends outward from the outermost trench among the plurality of trenches; and

one or more annular outer trenches that extend from the one main surface of the first-conduction-type semiconductor substrate to the first-conduction-type drift layer through the second-conduction-type extension region and surround all of the trenches, and

a second gap between the annular outer trench and the outermost trench or between the adjacent annular outer trenches when the plurality of annular outer trenches are provided is less than the first gap.

2. The semiconductor device according to claim 1,

wherein the plurality of trenches are arranged in the one main surface of the first-conduction-type semiconductor substrate in a stripe shape which extends in a direction perpendicular to a direction in which the trenches are arranged.

3. The semiconductor device according to claim 1,

wherein, when the second gap is b and the first gap is a, b/a<

0.8 is satisfied.

4. The semiconductor device according to claim 1,

wherein, when the second gap is b and the first gap is a, b/a<

0.6 is satisfied.

5. The semiconductor device according to claim 1,

wherein a surface of a portion of the second-conduction-type extension region which is interposed between the annular outer trench and the outermost trench or between the adjacent annular outer trenches when the plurality of annular outer trenches are provided is electrically connected to the metal electrode.

6. The semiconductor device according to claim 1,

wherein two or more annular outer trenches are provided.

7. The semiconductor device according to claim 1, further comprising:

an insulating film that covers the second-conduction-type extension region,

wherein the insulating film includes an opening through which a portion of the second-conduction-type extension region which is arranged outside the outermost annular outer trench is exposed, and

the second-conduction-type extension region is electrically connected to the metal electrode through the opening.

8. The semiconductor device according to claim 1, further comprising:

an insulating film that is provided on the one main surface of the first-conduction-type semiconductor substrate and insulates the metal electrode from the gate electrode,

wherein a portion which directly contacts the metal electrode and a portion which contacts the metal electrode with the insulating film interposed therebetween are alternately arranged on the one main surface of the first-conduction-type semiconductor substrate in the active region.

9. The semiconductor device according to claim 1,

wherein the ends of two adjacent trenches are connected to each other.