Integrated circuits including conductive structures through a substrate and methods of making the same

• US 9,059,262 B2
• Filed: 02/24/2011
• Issued: 06/16/2015
• Est. Priority Date: 02/24/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Yuan-Hung, Yang, Ku-Feng, Kuo, Pei-Ching, Chen, Hsin-Yu, Wu, Tsang-Jiuh, Chiou, Wen-Chih, Chung, Ming-Tsu
• Primary Examiner(s): SHINGLETON, MICHAEL B
• Application Number:
  US13/033,733
• Publication Number:
  US 20120217611A1
• Time in Patent Office: 1,573 Days
• Field of Search: 257/621, 257/E23.01, 257/E21.238, 257/737, 438/460
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

An integrated circuit includes a substrate having a first surface and a second surface. At least one conductive structure continuously extends through the substrate. At least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap.

Claims

1. An integrated circuit comprising:

a substrate having a first surface, a second surface, and an opening defined in the substrate, the opening extending from the first surface through the substrate to the second surface; and

at least one conductive structure continuously extending through the opening, wherein at least one sidewall of the at least one conductive structure is spaced from a sidewall of the opening by an air gap, the at least one conductive structure having a first width within the opening and adjacent to the first surface and a second width within the opening adjacent to the second surface, and the second width being greater than the first width, and a width of the air gap adjacent the first surface is greater than a width of the air gap adjacent the second surface.

2. The integrated circuit of claim 1, wherein the air gap has a first space adjacent to the first surface and a second space adjacent to the second surface, and the first space is larger than the second space.

3. The integrated circuit of claim 1, wherein the air gap is around the at least one conductive structure.

4. The integrated circuit of claim 1, further comprising:

at least one dielectric layer disposed around the at least one conductive structure.

5. The integrated circuit of claim 1, wherein the at least one conductive structure comprises at least one through-silicon-via (TSV) structure.

6. The integrated circuit of claim 1, further comprising:

an etch-stop layer disposed over the first surface of the substrate, wherein a surface of the at least one conductive structure is not level with a surface of the etch-stop layer.

11. The integrated circuit of claim 1, further comprising:

an interconnect structure over the substrate, wherein the interconnect structure is electrically connected to the at least one conductive structure.

12. The integrated circuit of claim 1, further comprising:

an interconnect structure over the substrate, wherein the interconnect structure is configured to seal the air gap.

13. The integrated circuit of claim 1, wherein the at least one conductive structure comprises a barrier material and a conductive material, wherein the barrier material comprises at least one of titanium or tantalum.

14. The integrated circuit of claim 4, wherein the dielectric material contacts at least a portion of the sidewall of the opening.

15. The integrated circuit of claim 1, further comprising:

an etch-stop layer disposed over the first surface of the substrate; and

an inter-layer dielectric (ILD) disposed between the etch-stop layer and the first surface of the substrate.

20. The integrated circuit of claim 1, wherein a difference between the width of the air gap adjacent the first surface and the width of the air gap adjacent the second surface is substantially equal to a difference between the second width and the first width.

7. An integrated circuit comprising:

a substrate having a first surface and a second surface;

at least one conductive structure continuously extending through the substrate, wherein at least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap, the air gap is around the at least one conductive structure, the air gap has a first space adjacent to the first surface and a second space adjacent to the second surface, and the first space is larger than the second space; and

an etch-stop layer disposed over the first surface of the substrate, wherein a surface of the at least one conductive layer is not level with a surface of the etch-stop layer.

8. The integrated circuit of claim 7, further comprising:

at least one dielectric layer disposed around the at least one conductive structure.

9. The integrated circuit of claim 7, wherein the at least one conductive structure comprises at least one through-silicon-via (TSV) structure.

10. The integrated circuit of claim 7, wherein the at least one conductive structure has a first width adjacent to the first surface and a second width adjacent to the second surface, and the second width is larger than the first width.

16. The integrated circuit of claim 7, further comprising:

an interconnect structure over the substrate, wherein the interconnect structure is electrically connected to the at least one conductive structure.

17. The integrated circuit of claim 7, further comprising:

an interconnect structure over the substrate, wherein the interconnect structure is configured to seal the air gap.

18. The integrated circuit of claim 7, wherein the at least one conductive structure comprises a barrier material and a conductive material, wherein the barrier material comprises at least one of titanium or tantalum.

19. The integrated circuit of claim 8, wherein the dielectric material contacts at least a portion of the sidewall of the substrate.