Pre-gate, source/drain strain layer formation

• US 9,059,286 B2
• Filed: 03/31/2014
• Issued: 06/16/2015
• Est. Priority Date: 03/08/2010
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Holt, Judson R., Ontalus, Viorel C., Tabakman, Keith H.
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Kim, Sun M
• Application Number:
  US14/230,087
• Publication Number:
  US 20140213029A1
• Time in Patent Office: 442 Days
• Field of Search: 438/269, 438/429, 438/222, 257/E21.618, 257/E21.619
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.

Claims

1. A method of producing a transistor, said method comprising:

forming a base layer on a substrate;

forming shallow trench isolation regions extending vertically through said base layer to said substrate;

forming a recess in said base layer between said shallow trench isolation regions such that a lower portion of said base layer remains between said shallow trench isolation regions;

forming a strain-producing layer in said recess on said base layer and extending laterally between and immediately adjacent to said shallow trench isolation regions;

removing at least one portion of said strain-producing layer to create an opening in said strain-producing layer and leave first and second portions of said strain-producing layer on said base layer, said first and second portions of said strain-producing layer comprising source and drain stressor regions of said transistor;

growing a channel region in said opening of said strain-producing layer from said base layer;

forming a gate insulator on and immediately adjacent to co-planar top surfaces of said channel region and said source and drain stressor regions adjacent to said channel region;

forming a gate conductor on said gate insulator after forming said source and drain stressor regions, said channel region, and said gate insulator, said gate conductor being formed so as to be on and immediately adjacent to said gate insulator and further above and vertically overlapping with said source and drain stressor regions such that only said gate insulator is stacked between said source and drain stressor regions and said gate conductor.

2. The method according to claim 1, said substrate comprising an insulator layer and said shallow trench isolation regions extending through said base layer to said insulator layer.

3. The method according to claim 1, said forming said strain-producing layer comprising epitaxially growing said strain-producing layer, and said growing of said channel region comprising epitaxially growing said channel region.

4. The method according to claim 1, said forming said strain-producing layer comprising forming a layer of one of SiGe and SiC.

5. The method according to claim 1, said growing said channel region in said opening of said strain-producing layer comprising forming sidewalls of said strain-producing layer and of said channel region where said strain-producing layer and said channel region meet, said sidewalls being perpendicular to planar surfaces of said top of said transistor.

6. The method according to claim 5, said channel region being narrower than each of said source and drain stressor regions.

7. A method of producing a transistor, said method comprising:

providing a silicon-on-insulator wafer comprising a semiconductor substrate, an insulator layer on said semiconductor substrate and a base layer on said insulator layer;

forming shallow trench isolation regions that extend vertically through said base layer to said insulator layer;

forming a recess in said base layer between said shallow trench isolation regions such that a lower portion of said base layer remains between said shallow trench isolation regions, said recess having a depth that is greater than one-half a thickness of said base layer;

forming a strain-producing layer in said recess on said base layer and extending laterally between and immediately adjacent to said shallow trench isolation regions such that said strain-producing layer is thicker than said lower portion;

removing at least one portion of said strain-producing layer to create an opening in said strain-producing layer and leave first and second portions of said strain-producing layer on said base layer, said first and second portions of said strain-producing layer comprising source and drain stressor regions of said transistor;

growing a channel region from said base layer in said opening of said strain-producing layer to a top of said strain-producing layer;

forming a gate insulator on and immediately adjacent to co-planar top surfaces of said channel region and said source and drain stressor regions adjacent to said channel region; and

forming a gate conductor on said gate insulator after forming said source and drain stressor regions, said channel region, and said gate insulator, said gate conductor being formed so as to be on and immediately adjacent to said gate insulator and further above and vertically overlapping with said source and drain stressor regions such that only said gate insulator is stacked between said source and drain stressor regions and said gate conductor.

8. The method according to claim 7, said channel region being narrow than each of said source and drain regions.

9. The method according to claim 7, said forming said strain-producing layer comprising epitaxially growing said strain-producing layer, and said growing of said channel region comprising epitaxially growing said channel region.

10. The method according to claim 7, said forming said strain-producing layer comprising forming a layer of one of SiGe and SiC.

11. The method according to claim 7, said growing said channel region in said opening of said strain-producing layer comprising forming sidewalls of said strain-producing layer and of said channel region where said strain-producing layer and said channel region meet, said sidewalls being perpendicular to planar surfaces of said top of said strain-producing layer, said planar surfaces being parallel to said gate insulator.