Photoconductor-on-active pixel device

• US 9,059,360 B2
• Filed: 03/31/2014
• Issued: 06/16/2015
• Est. Priority Date: 12/14/2010
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Gambino, Jeffrey P., Leidy, Robert K., Rassel, Richard J.
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Chin, Edward
• Application Number:
  US14/230,146
• Publication Number:
  US 20140209986A1
• Time in Patent Office: 442 Days
• Field of Search: 257/291, 257/292, 257/444, 257/E31.056, 257/E31.057, 257/331.06, 257/E31.084, 257/E31.085, 438/57, 438/98
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14665 Imagers using a photoconductor layer
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type

Abstract

A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.

Claims

1. A photoconductor-on-active pixel device comprising:

a first dielectric layer disposed on an intermediary layer;

a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer;

a second dielectric layer disposed on the first dielectric layer;

a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, the first capping layer including an etched upper surface that are flush with an upper surface of the second dielectric layer;

a second capping layer disposed on the first capping layer and a portion of the second dielectric layer;

an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion;

an intrinsic silicon layer disposed on the n-type doped silicon layer; and

a p-type doped silicon layer disposed on the intrinsic silicon layer.

2. The device of claim 1, wherein the intermediary layer includes a second conductive pad portion and a second interconnect portion.

3. The device of claim 2, wherein the device includes:

a first conductive via connecting the first conductive pad portion to the second conductive pad portion; and

a second conductive via connecting the first interconnect portion to the second interconnect portion.

4. The device of claim 1, wherein the intermediary layer is disposed on an active layer, the active layer including a field effect transistor device disposed on a substrate, and a third dielectric layer disposed on the field effect transistor device and the substrate.

5. The device of claim 1, wherein the first conductive pad portion and the first interconnect portion include aluminum.

6. The device of claim 3, wherein the first conductive via and the second conductive via include tungsten.

7. The device of claim 2, wherein the second conductive pad portion and a second interconnect portion include copper.

8. The device of claim 1, wherein the first capping layer and the second capping layer include a nitride material.

9. A photoconductor-on-active pixel device comprising:

a first dielectric layer disposed on an intermediary layer;

a first capping layer disposed on first dielectric layer, the first capping layer including an etched upper surface;

a first conductive pad portion and a first interconnect portion disposed on the first capping layer;

a second dielectric layer disposed on the first dielectric layer, the second dielectric layer including an upper surface that is flush with the etched upper surface of the first capping layer;

an n-type doped silicon layer disposed on the second dielectric layer, the first conductive pad portion, and the first interconnect portion;

an intrinsic silicon layer disposed on the n-type doped silicon layer; and

a p-type doped silicon layer disposed on the intrinsic silicon layer.

10. The device of claim 9, wherein the intermediary layer includes a second conductive pad portion and a second interconnect portion;

and the device includes;

a first conductive via connecting the first conductive pad portion to the second conductive pad portion; and

a second conductive via connecting the first interconnect portion to the second interconnect portion.

11. The device of claim 9, wherein the intermediary layer is disposed on an active layer, the active layer including a field effect transistor device disposed on a substrate, and a third dielectric layer disposed on the field effect transistor device and the substrate.

12. A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure comprising:

a first dielectric layer disposed on an intermediary layer;

a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer;

a second dielectric layer disposed on the first dielectric layer;

a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, the first capping layer including an etched upper portion that is flush with an upper surface of the second dielectric layer;

a second capping layer disposed on the first capping layer and a portion of the second dielectric layer;

an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion;

an intrinsic silicon layer disposed on the n-type doped silicon layer; and

a p-type doped silicon layer disposed on the intrinsic silicon layer.

13. The design structure of claim 12, wherein the intermediary layer includes a second conductive pad portion and a second interconnect portion.

14. The design structure of claim 13, wherein the device includes:

a first conductive via connecting the first conductive pad portion to the second conductive pad portion; and

a second conductive via connecting the first interconnect portion to the second interconnect portion.

15. The design structure of claim 12, wherein the design structure comprises a netlist.

16. The design structure of claim 12, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.