Antenna arrangement for transmitting signals

• US 9,059,503 B2
• Filed: 10/29/2010
• Issued: 06/16/2015
• Est. Priority Date: 10/29/2009
• Status: Active Grant

• Current Assignee: Technische Universitã¤T Dresden
• Original Assignee: Technische Universitã¤T Dresden
• Inventors: Plettemeier, Dirk, Jenning, Michael, Liang, Ting-Jung
• Primary Examiner(s): Ho, Tan
• Application Number:
  US13/504,255
• Publication Number:
  US 20130009848A1
• Time in Patent Office: 1,691 Days
• Field of Search: 343/767, 343/893, 257/659, 257/679
• US Class Current: 1/1
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01Q 1/2283 mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 21/06 Arrays of individually energised antenna units similarly polarised and spaced apart

Abstract

An antenna arrangement for transmitting signals has improved directional characteristics and a higher antenna gain, is simple to produce, and is robust and cost-effective. The antenna arrangement has a plurality of planes, and a plurality of individual antennas are arranged in each plane.

Claims

1. An antenna arrangement for transmitting signals to and/or from a semiconductor chip, comprising a first sub-arrangement of individual antennas arranged in a first plane spaced from an outer surface of the semiconductor chip, and a second sub-arrangement of individual antennas arranged in one or more other planes, with a plurality of individual antennas arranged in each of said one or more other planes, wherein each antenna is connected to a separate control unit or some of the individual antennas are interconnected in a cluster controlled by a common control unit, and wherein electrical amplitudes and phases of all individual antennas and/or clusters are controlled simultaneously and independently of one another in a dynamic operating mode.

2. The antenna arrangement according to claim 1, wherein orientation of the antennas in a plane is the same.

3. The antenna arrangement according to claim 1, wherein orientation of the antennas in a plane is different.

4. The antenna arrangement according to claim 1, wherein orientation of the antennas between two adjacent planes is the same.

5. The antenna arrangement according to claim 1, wherein orientation of the antennas between two adjacent planes is different.

6. The antenna arrangement according to claim 1, wherein antennas of two adjacent planes are arranged congruent or offset to one another.

7. The antenna arrangement according to claim 1, wherein the planes have a circular or n-cornered base area with n≧

3.

8. The antenna arrangement according to claim 1, wherein the planes are arranged one above the other, forming a cuboid or a pyramid frustum structure.

9. The antenna arrangement according to claim 1, wherein the coupling of the antenna arrangement to the chip occurs by contacts, inductively, or capacitively.

10. The antenna arrangement according to claim 1, wherein the antenna arrangement is arranged indirectly on the chip or in a housing part covering the chip like a cover.

11. The antenna arrangement according to claim 1, wherein the antenna arrangement and a supply network for controlling the individual antennas and/or clusters are located in a common housing for the semiconductor chip.

12. The antenna arrangement according to claim 1, wherein at least two of the individual antennas are of different types.

13. The antenna arrangement according to claim 12, wherein the at least two individual antennas of different types are in a same plane.

14. The antenna arrangement according to claim 12, wherein the different types include a patch antenna and a vivaldi antenna.

15. The antenna arrangement according to claim 12, wherein the different types include a cavity-backed dipole antenna, and a vivaldi antenna.

16. The antenna arrangement according to claim 1, wherein at least one of the individual antennas of the second sub-arrangement comprises a vivaldi antenna.

17. The antenna arrangement according to claim 1, wherein the first sub-arrangement comprises patch antennas or loop antennas, and the second sub-arrangement comprises vivaldi antennas.

18. The antenna arrangement according to claim 1, wherein the first sub-arrangement is located above the semi-conductor chip, and the second sub-arrangement is located along a side of the semiconductor chip.

19. The antenna arrangement according to claim 1, wherein the individual antennas of the first sub-arrangement are selected from the group consisting of:

patch antennas, dielectric resonator antennas, loop antennas, rhombic antennas, printed dipoles, yagi antennas, cavity-backed structures and vias serving as horn antennas.

20. The antenna arrangement according to claim 19, wherein the individual antennas of the second sub-arrangement are selected from the group consisting of:

widened slot antennas, vivaldi antennas, dipoles, yagi antennas, laterally mounted patch antennas, and dielectric resonator antennas.