Variable frequency oscillator with specialized inverter stages

• US 9,059,660 B1
• Filed: 12/17/2013
• Issued: 06/16/2015
• Est. Priority Date: 12/17/2013
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Davies, Andrew D., Ficke, Joel T., Friend, David M., Kesselring, Grant P., Strom, James D.
• Primary Examiner(s): Chang, Joseph
• Assistant Examiner(s): Shin, Jeffrey
• Application Number:
  US14/109,364
• Publication Number:
  US 20150171790A1
• Time in Patent Office: 546 Days
• Field of Search: 331/36.C, 331/57, 331/143, 331/175, 331/177.R
• US Class Current: 1/1
• CPC Class Codes: H03B 5/124 the means comprising a voltage dependent capacitance
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/354 Astable circuits

Abstract

A variable frequency oscillator device includes a first inverter stage that is designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provides a respective amount of current that is responsive to a control signal and to a dampening signal. A second inverter stage is designed to generate a first inverted signal from the sawtooth signal of the first inverter stage. A third inverter stage is designed to generate a second inverted signal from the first inverted signal, and dampen a signal transition rate for the first inverted signal based upon the control signal.

Claims

1. A variable frequency oscillator device comprising:

a first inverter stage having;

at least one capacitor having a parasitic capacitance to alternating current (AC) couple the first inverter stage to an output node;

a push pull circuit configured to generate a sawtooth signal for capacitive coupling to the output node by;

inverting an input signal, and

charging and discharging, responsive to a control signal, an oscillator capacitance predominantly derived from the parasitic capacitance of the at least one capacitor;

a second inverter stage to generate a first inverted signal from the output node of the first inverter stage, the second inverter stage including a resistive feedback path to, in response to changes in the control signal, change resistance values; and

a third inverter stage designed to generate a second inverted signal from the first inverted signal and to provide the second inverted signal as the input signal.

2. The device of claim 1, wherein the third inverter stage is designed to dampen a signal transition rate of the second inverted signal in response to the control signal.

3. The device of claim 1, wherein the third inverter stage includes two transistors designed to dampen a signal transition rate for the first inverted signal based upon the control signal.

4. The device of claim 3, wherein the two transistors have gates tied to the control signal and wherein the third inverter stage further includes two additional transistors having gates tied to an output of the third inverter stage.

5. A variable frequency oscillator device comprising:

a first inverter stage designed to invert an input signal to generate a sawtooth signal by charging and discharging a capacitor using current sources that each provide a respective amount of current that is responsive to a control signal and to a dampening signal;

a second inverter stage designed to generate a first inverted signal from the sawtooth signal of the first inverter stage; and

a third inverter stage designed to;

generate a second inverted signal from the first inverted signal, and

dampen a signal transition rate for the first inverted signal based upon the control signal.

6. The device of claim 5, wherein the third inverter stage includes two transistors having gates tied to the control signal.

7. The device of claim 6, wherein the third inverter stage further includes two additional transistors having gates tied to an output of the third inverter stage.

8. The device of claim 5, wherein the capacitor is configured to:

provide capacitive coupling between the first and second inverted stages; and

provide an oscillator capacitance predominantly derived from a parasitic capacitance of the capacitor.

9. The device of claim 5, wherein the second inverter stage includes a resistive feedback path.

10. The device of claim 5, wherein the second inverter stage includes a resistive feedback path that is designed to change resistance values in response to changes in the control signal.

11. A method comprising:

generating, using a first inverter stage, a sawtooth signal by;

inverting an input signal, and

charging and discharging, responsive to a control signal, an oscillator capacitance predominantly derived from a parasitic capacitance of at least one capacitor;

capacitively coupling, using the at least one capacitor, the sawtooth signal to an output node;

generating, using a second inverter stage, a first inverted signal from the output node;

generating, using a third inverter stage, a second inverted signal from the first inverted signal;

providing the second inverted signal as the input signal; and

dampening, in response to the control signal, a signal transition rate for the third inverter stage.

12. The method of claim 11, further comprising adjusting a resistance of a resistive feedback path for the second inverter stage in response to the control signal.