Equalization circuit and equalization system

• US 9,059,769 B2
• Filed: 06/12/2012
• Issued: 06/16/2015
• Est. Priority Date: 09/22/2011
• Status: Active Grant

• Current Assignee: IPGoal Microelectronics (Sichuan) Co., Ltd.
• Original Assignee: IPGoal Microelectronics (Sichuan) Co., Ltd.
• Inventors: Wu, Zhaolei, Li, Lei
• Primary Examiner(s): Jones, Stephen E
• Application Number:
  US13/494,028
• Publication Number:
  US 20130076329A1
• Time in Patent Office: 1,099 Days
• Field of Search: 333/28.R, 375/229
• US Class Current: 1/1
• CPC Class Codes: H04B 1/12 Neutralising, balancing, or compensation arrangements
• CPC Class Codes: H04B 3/04 Control of transmission; Equalising

Abstract

An equalization circuit, includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first regulating circuit, a second regulating circuit, and a bias voltage generating circuit. The bias voltage generating circuit is connected with both the first regulating circuit and the second regulating circuit. The first regulating circuit includes a first field effect transistor (FET), a second FET, a third FET, a fourth FET, a first resistor connected with the first FET, a second resistor connected with the second FET, a third resistor connected with the third FET, a fourth resistor connected with the fourth FET, a fifth resistor connected with the third FET, a sixth resistor connected with the fourth FET, a first capacitor connected with the third FET, and a second capacitor connected with the fourth FET. An equalization system is further provided.

Claims

1. An equalization circuit, comprising a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first regulating circuit connected with said first input terminal and said second input terminal for regulating a frequency-amplitude characteristic of input signals at said first input terminal and said second input terminal, a second regulating circuit connected with said first regulating circuit, said first output terminal and said second output terminal, and a bias voltage generating circuit, wherein said bias voltage generating circuit is respectively connected with said first regulating circuit and said second regulating circuit, said first regulating circuit comprises a first field effect transistor (FET) connected with said second input terminal, a second FET connected with said first FET, a third FET, a fourth FET connected with said third FET, a first resistor connected with said first FET, a second resistor connected with said second FET, a third resistor connected with said third FET, a fourth resistor connected with said fourth FET, a fifth resistor connected with said third FET and said third resistor, a sixth resistor connected with said fourth FET and said fourth resistor, a first capacitor connected with said third FET and said fifth resistor, and a second capacitor connected with said fourth FET and said sixth resistor.

2. The equalization circuit, as recited in claim 1, wherein a gate electrode of said first FET is connected with said second output terminal, a gate electrode of said second FET is connected with said first input terminal, a drain electrode of said first FET is connected with a first terminal of said first resistor, a first terminal of said third resistor, and a gate electrode of a fifth FET in said second regulating circuit, a drain electrode of said second FET is connected with a first terminal of said second resistor, a first terminal of said fourth resistor, and a gate electrode of a sixth FET in said second regulating circuit, both a source electrode of said first FET and a source electrode of said second FET are connected with a drain electrode of an eighth FET in said bias voltage generating circuit.

3. The equalization circuit, as recited in claim 1, wherein a gate electrode of said third FET is connected with a first terminal of said fifth resistor and a first terminal of said first capacitor, a drain electrode of said third FET is connected with a second terminal of said fifth resistor and a second terminal of said third resistor, a gate electrode of said fourth FET is connected with a first terminal of said sixth resistor and a first terminal of said second capacitor, a drain electrode of said fourth FET is connected with a second terminal of said sixth resistor, and a second terminal of said fourth resistor, both a source electrode of said third FET and a source electrode of said fourth FET are connected with a drain electrode of a ninth FET in said bias voltage generating circuit.

4. The equalization circuit, as recited in claim 1, wherein said second regulating circuit comprises a fifth FET connected with said first FET and said first resistor, a sixth FET connected with said second FET and said second resistor, a seventh resistor connected with said fifth FET, an eighth resistor connected with said sixth FET, a ninth resistor connected with said fifth FET and said sixth FET, and a third capacitor connected with said ninth resistor.

5. The equalization circuit, as recited in claim 4, wherein a drain electrode of said fifth FET is connected with a first terminal of said seventh resistor and said second output terminal, a source electrode of said fifth FET is connected with a first terminal of said ninth resistor, a first terminal of said third capacitor, and a drain electrode of a tenth FET in said bias voltage generating circuit, a drain electrode of said sixth FET is connected with a first terminal of said eighth resistor and said first output terminal, a source electrode of said sixth FET is connected with a second terminal of said ninth resistor, a second terminal of said third capacitor, and a drain electrode of an eleventh FET in said bias voltage generating circuit.

6. The equalization circuit, as recited in claim 1, wherein said bias voltage generating circuit comprises a seventh FET, an eighth FET connected with said first FET and said second FET, a ninth FET connected with said third FET and said fourth FET, a tenth FET connected with said ninth resistor, and an eleventh FET connected with said tenth FET;

wherein a gate electrode of said seventh FET, a drain electrode of said seventh FET, a gate electrode of said eighth FET, a gate electrode of said ninth FET, a gate electrode of said tenth FET, and a gate electrode of said eleventh FET are all connected with a bias voltage terminal.

7. The equalization circuit, as recited in claim 6, wherein both a second terminal of said first resistor and a second terminal of said second resistor are connected with a power source terminal;

a source electrode of said seventh FET, a source electrode of said eighth FET, a source electrode of said ninth FET, a source electrode of said tenth FET, and a source electrode of said eleventh FET are all connected with a ground terminal.

8. An equalization system, comprising a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first regulating circuit connected with said first input terminal and said second input terminal for regulating a frequency-amplitude characteristic of differential signals at said first input terminal and said second input terminal, a second regulating circuit connected with said first regulating circuit for obtaining an appropriate regulating range of a transmission signal, and a bias voltage generating circuit for providing a constant current for said equalization system to work normally, wherein said bias voltage generating circuit is respectively connected with said first regulating circuit and said second regulating circuit;

wherein said first regulating circuit comprises a first field effect transistor (FET), a second FET connected with said first FET, a third FET, a fourth FET connected with said third FET, a first resistor connected with said first FET, a second resistor connected with said second FET, a third resistor connected with said third FET, a fourth resistor connected with said fourth FET, a fifth resistor connected with said third FET and said third resistor, a sixth resistor connected with said fourth FET and said fourth resistor, a first capacitor connected with said third FET and said fifth resistor, and a second capacitor connected with said fourth FET and said sixth resistor.

9. The equalization system, as recited in claim 8, wherein said second regulating circuit comprises a fifth FET connected with said first FET and said first resistor, a sixth FET connected with said second FET and said second resistor, a seventh resistor connected with said fifth FET, an eighth resistor connected with said sixth FET, a ninth resistor connected with said fifth FET and said sixth FET, and a third capacitor connected with said ninth resistor, wherein said bias voltage generating circuit comprises a seventh FET, an eighth FET connected with said first FET and said second FET, a ninth FET connected with said third FET and said fourth FET, a tenth FET connected with said fifth resistor, and an eleventh FET connected with said sixth FET.