Memory management for an intelligent electronic device

• US 9,063,181 B2
• Filed: 12/28/2007
• Issued: 06/23/2015
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: EI Electronics LLC (Hubbell, Inc.)
• Original Assignee: Electro Industries/Gaugetech
• Inventors: Banker, Patricia E.
• Primary Examiner(s): Li, Aimee
• Assistant Examiner(s): SIMONETTI, NICHOLAS J
• Application Number:
  US11/965,798
• Publication Number:
  US 20080195794A1
• Time in Patent Office: 2,734 Days
• Field of Search: 707/999.2, 707/999.205, 707/999.206, 711133-135, 711/154, 711/156, 711159-160, 711/103
• US Class Current: 1/1
• CPC Class Codes: G01R 19/2513 Arrangements for monitoring electric power systems, e.g. power lines or loads; Logging
• CPC Class Codes: G01R 21/133 by using digital technique
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A device and method are provided for managing flash memory of an intelligent electronic device (IED) to maximize the IED life. The IED includes at least one sensor for sensing at least one electrical parameter distributed to a load. At least one analog-to-digital converter is coupled to the at least one sensor for converting an analog signal output from the at least one sensor to digital data. A processing unit is coupled to the at least one analog-to-digital converter to receive the digital data and store the digital data in a memory. The memory includes sectors configured to store the digital data. The processing unit stores the digital data in each of the sectors and equalizes usage of each sector over time by equalizing a number of erases for each of the sectors over time.

Claims

1. An intelligent electronic device comprising:

a sensor configured for sensing an electrical parameter distributed to a load;

an analog-to-digital converter coupled to the sensor, the analog-to-digital converter configured for converting an analog signal of the electrical parameter to digital data, wherein the digital data includes at least one log of the sensed electrical parameter;

a flash memory device including a plurality of sectors, wherein the plurality of sectors are erased during manufacture of the intelligent electronic device;

a random access memory (RAM) device; and

a processing unit coupled to the analog-to-digital converter;

wherein, after the plurality of sectors of the flash memory device are erased during manufacture of the intelligent electronic device, the RAM device creates a sector header;

wherein, after creating the sector header and before the sensor is operated, the RAM device writes the sector header into each of the plurality of sectors of the flash memory device;

wherein the processing unit is configured to receive the at least one log and store the at least one log in the flash memory device;

wherein the processing unit is further configured to store the at least one log in at least one of the sectors of the flash memory device to equalize usage of each of the plurality of sectors over time;

wherein the processing unit is further configured to assign a unique sequence number to each of the sector headers associated with the sectors within which the at least one log is stored, the unique sequence numbers being assigned by the processing unit in time sequence such that sorting the unique sequence numbers allows the processing unit to arrange the sectors in correct time sequence; and

wherein the processing unit is further configured to construct a log directory for associating each of the plurality of sectors with each of the at least one log;

wherein the processing unit is further configured to determine an error count for each of the plurality of sectors and select a next sector in which to save data based on the error count.

2. The device as in claim 1, wherein the flash memory device is removable.

3. The device as in claim 1, wherein the processing unit is configured to manage wear of the plurality of sectors so that the number of erases for each of the plurality of sectors is equalized over time.

4. The device as in claim 1, wherein the RAM device is further configured to write into each sector header an erase count, assignment, sequence number, and at least one checksum.

5. The device as in claim 4, wherein the assignment comprises erased, available, and in use.

6. The device as in claim 5, wherein the assignment comprises released and error, wherein the assignment of error is equivalent to an assignment of dead.

7. The device as in claim 6, wherein the at least one checksum includes a first checksum that is valid when the assignment is in use and a second checksum when the assignment is released.

8. The device of claim 1, wherein the RAM device is further configured to write into each sector header an assignment identifying the contents of that sector.

9. The device as in claim 8, wherein the assignment comprises erased, available, and in use.

10. The device as in claim 9, wherein the assignment comprises released and error, wherein the assignment of error is equivalent to an assignment of dead and wherein the in use assignment includes a plurality of values distinguishing one use from another.

11. The device as in claim 10, wherein the processing unit is further configured to construct a sector directory for each of the plurality of sectors for indicating the content of each of the sectors.

12. The device as in claim 11, wherein the constructed sector directory is located in a different memory than the at least one log associated with the constructed sector directory.

13. The device as in claim 1, wherein the determined error count is stored in non-volatile memory.

14. The device as in claim 1, wherein the processing unit is further configured to determine an erase count for each of the plurality of sectors and select the next sector in which to save data from the available sectors based on the error count and erase count.

15. The device as in claim 14, wherein the determined erase count is stored in non-volatile memory.

16. The device as in claim 14, wherein the processing unit is further configured to select from the available sectors the next sector in which to save data based on the determined error and erase counts together.

17. The device as in claim 16, wherein the determined error count and determined erase count are stored in non-volatile memory.

18. The device as in claim 16, wherein the processing unit is further configured to store the digital data in at least one sector selected from a group of sectors with the lowest error counts and the sector having the lowest erase count of the group.

19. The device as in claim 1, wherein the RAM device writes an assignment into each sector header, the assignment in each sector header configured to indicate a state of the respective sector as one of erased, available, in use, released, and dead;

wherein an assignment of one of erased, available, in use, and released designates sectors that are operational and an assignment of dead designates sectors that are not operational;

wherein the processing unit is configured to store the at least one log in at least one of the operational sectors of the flash memory device; and

wherein the processing unit is further configured to select the next sector based on the operational sector with the lowest error count.

20. A method for managing a flash memory in an intelligent electronic device, the flash memory comprising a plurality of independently-erasable sectors to be used as a set for storing data files, the method comprising the steps of:

erasing the plurality of independently-erasable sectors of the flash memory during manufacture of the intelligent electronic device;

after erasing the plurality of independently-erasable sectors during the manufacture of the intelligent electronic device, creating a sector header;

after creating the sector header, writing the sector header in each of the plurality of independently-erasable sectors of the flash memory device;

after writing the sector header in each of the plurality of independently-erasable sectors, sensing a parameter of electrical power distributed to a load;

converting the sensed parameter from an analog signal to digital data, the digital data including at least one data file to be stored in the flash memory;

determining an erase count of at least one of the plurality of independently-erasable sectors;

determining the at least one independently-erasable sector having the lowest erase count;

assigning a unique sequence number to each of the sector headers associated with at least one of the plurality of independently-erasable sectors within which the at least one data file is stored, the unique sequence numbers being assigned in time sequence such that sorting the unique sequence numbers allows the independently-erasable sectors to be arranged in correct time sequence;

constructing a log directory for associating each of the plurality of independently erasable sectors with each of the at least one data file;

determining an error count for each of the plurality of independently-erasable sectors; and

selecting a next independently-erasable sector in which to save data, the next independently-erasable sector being selected based on a group of independently-erasable sectors with the lowest error count and the independently-erasable sector of the group with the lowest erase count.

21. The method as in claim 20, further comprising configuring each sector header of the independently-erasable sectors to store an erase count of a corresponding independently erasable sector.

22. The method as in claim 20, further comprising configuring each sector header to store an assignment of a corresponding independently-erasable sector.

23. The method as in claim 22, wherein the assignment comprises erased, available, in use, released, and error, wherein the assignment of error is equivalent to an assignment of dead, and wherein the assignment of in use includes a plurality of values distinguishing one use from another.

24. The method as in claim 20, further comprising determining the sector assignment and the sequence number for at least one of the plurality of independently-erasable sectors and generating a sector directory.

25. The method as in claim 24, further comprising generating a file directory including determining the independently-erasable sectors belonging to the at least one data file, sorting the independently-erasable sectors into oldest to newest order using the sequence numbers, and determining file sizes, wherein the file size is determined by searching for the end of the at least one data file.

26. The method of claim 25, wherein the sector and file directories are located in a memory that is different from a memory in which data referenced by the sector and file directories is stored.

27. The method of claim 24, wherein the sector directory comprises means for the intelligent electronic device to determine the contents of every independently-erasable sector.

28. The method as in claim 20, further comprising the step of writing an assignment into each sector header, the assignment in each sector header configured to indicate a state of the respective independently-erasable sector as one of erased, available, in use, released, and dead, an assignment of one of erased, available, in use, and release designating independently-erasable sectors that are operational and an assignment of dead designating independently-erasable sectors that are not operational;

and

wherein the step of selecting the next independently-erasable sector in which to store the data includes selecting an operational independently-erasable sector.