Direct memory access for loopback transfers in a media controller architecture

• US 9,063,561 B2
• Filed: 11/23/2010
• Issued: 06/23/2015
• Est. Priority Date: 05/06/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Noeldner, David R., Bratvold, Michael
• Primary Examiner(s): Rutz, Jared
• Assistant Examiner(s): Ayash, Marwan
• Application Number:
  US12/952,202
• Publication Number:
  US 20110131374A1
• Time in Patent Office: 1,673 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/00 Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

Described embodiments provide for transferring data from one location to another location in a memory of a media controller. A transmit data path and a receive data path of the media controller are linked with a generic direct memory access (GDMA). The transmit data path includes a transmit (TX) buffer and the receive data path includes a receive (RX) buffer. The GDMA is programmed with a total transfer count and a transfer mode. The GDMA processes the movable data based on the total transfer count and the transfer mode by converting one or more portions of the movable data in the TX buffer into a predefined frame structure defined with status entries, which translates frames of the moveable data between the TX data path and the RX data path and synchronizes the movable data between the TX buffer and the RX buffer with the status entries.

Claims

1. A method of transferring data from one location to another location in a memory of a media controller, the method comprising:

arranging, in a media controller, a link protocol core in parallel with a buffer subsystem, the link protocol core exposing data in the memory to an external device coupled to the media controller by a communications link;

linking a transmit data path and a receive data path of the media controller with a generic direct memory access (GDMA), the transmit data path having a transmit (TX) buffer and the receive data path having a receive (RX) buffer;

programming the GDMA with a total transfer count and a transfer mode; and

processing, by the GDMA, the movable data based on the total transfer count and the transfer mode, the processing comprising;

isolating the link protocol core from the transmit and receive data paths of the media controller;

converting one or more portions of the movable data in the TX buffer into a predefined frame structure defined with status entries, thereby translating data frames of the movable data between the TX data path associated with the TX buffer and the RX data path associated with the RX buffer; and

synchronizing the movable data between the TX buffer and the RX buffer with the status entries;

wherein the GDMA is configured to place the link protocol core, coupled to the transmit and receive data paths of the media controller, into an idle mode where the link protocol core does not respond to data transfer requests during GDMA operations.

2. The method as recited in claim 1, wherein the TX buffer is coupled to a TX DMA for transferring data from the memory to the TX buffer, and the RX buffer is coupled to an RX DMA for transferring data from the RX buffer to the memory.

3. The method as recited in claim 1, wherein, for the transferring of the data, the transfer mode is a loopback mode.

4. The method as recited in claim 3, comprising:

placing movable data from the memory into the TX buffer;

checking, based on the TX data available value, whether movable data exists in the TX buffer, and

if movable data exists,

transferring a current portion of the movable data from the TX buffer to the RX buffer via the GDMA;

adjusting the total transfer count; and

repeating the transferring and the adjusting until the total transfer count reaches a threshold.

5. The method as recited in claim 4, comprising creating a corresponding status entry after a predefined number of portions of movable data are transferred between the TX buffer and the RX buffer.

6. The method as recited in claim 1, wherein, for the transferring of the data, the transfer mode is a write-same mode.

7. The method as recited in claim 6, comprising:

loading the TX buffer with a data block as movable data, the data block having multiple corresponding write destinations;

pointing a wrap pointer of the TX buffer to a corresponding boundary of the data block, thereby repeating loading of the TX buffer with the data block for each transfer of movable data;

transferring, regardless of the TX data available value, the movable data from the TX buffer to the RX buffer, via the GDMA, wherein the RX buffer transfers the data to a corresponding location in the memory based on the total transfer count;

adjusting the total transfer count for each transferred portion of the movable data; and

ending the transfer of the one or more portions when the total transfer count reaches a threshold.

8. The method as recited in claim 1, wherein, for the transferring of the data, the transfer mode is a memory write test mode.

9. The method as recited in claim 8, comprising:

loading the GDMA with a data pattern;

generating, by the GDMA, a test pattern from the data pattern as movable data based on a pattern option;

transferring one or more portions of the test pattern to the RX buffer based on the total transfer count, wherein the RX buffer transfers the data to corresponding locations in the memory;

adjusting the total transfer count for each transferred portion of the movable data; and

ending the transfer of the one or more portions when the total transfer count reaches a threshold.

10. The method as recited in claim 9, comprising checking the test pattern in the memory.

11. The method as recited in claim 9, wherein, for generating the test pattern, the pattern option is selected from the group consisting of i) left-rotate user pattern option, ii) right-rotate user pattern option, iii) add user pattern option, and iv) byte-wise add user pattern option.

12. The method as recited in claim 1, wherein, for the transferring of the data, the transfer mode is a memory read test mode.

13. The method as recited in claim 12, comprising:

loading the GDMA with a data pattern;

generating a test pattern from the data pattern as movable data based on a pattern option;

transferring a current portion of the test pattern in a corresponding location in the memory through the TX buffer for a current value of the total transfer count;

checking, by the GDMA, validity of the transferred current portion based on a corresponding portion of the test pattern, and if the transferred current portion is invalid, detecting a data mismatch.

14. The method as recited in claim 13 further comprising, if the transferred current portion is valid, discarding the current portion.

15. The method as recited in claim 1, comprising:

adjusting the current total transfer count to a subsequent total transfer count for each transferred current portion of the movable data; and

ending when the total transfer count reaches a threshold.

16. A non-transitory machine-readable storage medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method of transferring data from one location to another location in a memory of a media controller, the method comprising:

arranging, in a media controller, a link protocol core coupled to an external device over a communication link, the link protocol core arranged in parallel with a buffer subsystem;

linking a transmit data path and a receive data path of the media controller with a generic direct memory access (GDMA), the transmit data path having a transmit (TX) buffer and the receive data path having a receive (RX) buffer;

programming the GDMA with a total transfer count and a transfer mode; and

processing, by the GDMA, the movable data based on the total transfer count and the transfer mode, the processing comprising;

isolating the link protocol core from the transmit and receive data paths of the media controller;

converting one or more portions of the movable data in the TX buffer into a predefined frame structure defined with the status entries, thereby translating data frames of the moveable data between the TX data path associated with the TX buffer and the RX data path associated with the RX buffer; and

synchronizing the movable data between the TX Buffer and the RX buffer with the status entries;

wherein the GDMA places the link protocol core, coupled to the transmit and receive data paths of the media controller, into an idle mode where the link protocol core does not respond to the external device during GDMA operations.

17. A media controller, comprising:

a transmit data path having a transmit (TX) buffer, the transmit data path coupled to a buffer subsystem at an input of the TX buffer and a link protocol core at an output of the TX buffer;

a receive data path having a receive (RX) buffer, the receive data path coupled to the link protocol core at an input of the RX buffer and the buffer subsystem at an output of the RX buffer;

a generic direct memory access (GDMA), coupled between the transmit data path and the receive data path in parallel with the link core protocol and the buffer subsystem, the GDMA configured to transfer data from one location to another location in a memory of the media controller, wherein the media controller;

i) receives a total transfer count and a transfer mode,

ii) processes the movable data based on the total transfer count and the transfer mode, by

(1) converting one or more portions of the movable data in the TX buffer into a predefined frame structure defined with status entries generated by the GDMA, thereby translating data frames of the movable data between the TX data path associated with the TX buffer and the RX data path associated with the RX buffer; and

(2) synchronizing the movable data between the TX Buffer and the RX buffer with the status entries;

wherein the TX buffer is coupled to a TX DMA for transferring data from the memory to the TX buffer, and the RX buffer is coupled to an RX DMA for transferring data from the RX buffer to the memory, and wherein the GDMA is configured to place the link protocol core, coupled to the transmit and receive data paths of the media controller, into an idle mode where the link protocol core ignores data transfer requests from an external device over a communications link coupled to the link protocol core during GDMA operations thereby isolating the link protocol core from the transmit and receive data paths of the media controller.

18. The media controller as recited in claim 17, wherein, for the transferring of the data, the transfer mode is one of:

a loopback mode, a write-same mode, a memory write test mode and a memory read test mode.

19. The media controller as recited in claim 17, wherein the media controller is coupled to a storage media comprising a Redundant Array of Independent Disks (RAID) array.

20. The media controller as recited in claim 19, wherein the RAID array comprises at least one of a solid state disk (SSD), a hard disk drive (HDD), or a hybrid magnetic and solid state storage system.