Large multiplier for programmable logic device
First Claim
1. For use in a programmable logic device having a plurality of specialized processing blocks, each of said specialized processing blocks having at least four n-by-n multipliers arranged in four-multiplier units, a method of performing a signed 3n-by-3n multiplication operation, said method comprising:
- performing a 2n-by-2n multiplication using four of said n-by-n multipliers in a first of said four-multiplier units;
performing an n-by-n multiplication using one of said n-by-n multipliers in a second of said four-multiplier units; and
performing first and second 2n-by-n multiplications in a third of said four-multiplier units, using two of said n-by-n multipliers for each of said 2n-by-n multiplications;
wherein;
in each of said multiplications, multiplicands representing n most significant bits are treated as signed operands and multiplicands representing n least significant bits are forced to be unsigned;
said method further comprising;
shifting a second partial product of each of said 2n-by-n multiplications to align it with a first partial product of each of said 2n-by-n multiplications for addition within said third four-multiplier unit; and
adding results of said multiplications from said first, second and third four-multiplier units.
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Abstract
A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. Circuitry that controls when an input is signed or unsigned facilitates complex arithmetic.
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Citations
21 Claims
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1. For use in a programmable logic device having a plurality of specialized processing blocks, each of said specialized processing blocks having at least four n-by-n multipliers arranged in four-multiplier units, a method of performing a signed 3n-by-3n multiplication operation, said method comprising:
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performing a 2n-by-2n multiplication using four of said n-by-n multipliers in a first of said four-multiplier units; performing an n-by-n multiplication using one of said n-by-n multipliers in a second of said four-multiplier units; and performing first and second 2n-by-n multiplications in a third of said four-multiplier units, using two of said n-by-n multipliers for each of said 2n-by-n multiplications;
wherein;in each of said multiplications, multiplicands representing n most significant bits are treated as signed operands and multiplicands representing n least significant bits are forced to be unsigned;
said method further comprising;shifting a second partial product of each of said 2n-by-n multiplications to align it with a first partial product of each of said 2n-by-n multiplications for addition within said third four-multiplier unit; and adding results of said multiplications from said first, second and third four-multiplier units. - View Dependent Claims (2, 3, 4, 5)
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6. A programmable logic device having a plurality of specialized processing blocks, each of said specialized processing blocks having at least four n-by-n multipliers arranged in four-multiplier units, said programmable logic device being configured to perform a signed 3n-by-3n multiplication operation and comprising:
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four of said n-by-n multipliers in a first of said four-multiplier units configured to perform a 2n-by-2n multiplication; one of said n-by-n multipliers in a second of said four-multiplier units configured to perform an n-by-n multiplication; a third of said four-multiplier units configured to perform first and second 2n-by-n multiplications, using two of said n-by-n multipliers for each of said 2n-by-n multiplications; circuitry at multiplicand inputs of at least one of said multipliers for selectably forcing at least one of said inputs to be unsigned; a shifter configured to shift a second partial product of each of said 2n-by-n multiplications to align it with a first partial product of each of said 2n-by-n multiplications for addition within said third four-multiplier unit; and circuitry configured to add results of said multiplications from said first, second and third four-multiplier units. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. A data storage medium encoded with machine-executable instructions for performing a method of programmably configuring a programmable logic device to perform a signed 3n-by-3n multiplication operation, wherein said programmable logic device has a plurality of specialized processing blocks, each of said specialized processing blocks having at least four n-by-n multipliers arranged in four-multiplier units, said instructions comprising:
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instructions for configuring four of said n-by-n multipliers in a first of said four-multiplier units to perform a 2n-by-2n multiplication; instructions for configuring one of said n-by-n multipliers in a second of said four-multiplier units to perform an n-by-n multiplication; instructions for configuring a third of said four-multiplier units to perform first and second 2n-by-n multiplications, using two of said n-by-n multipliers for each of said 2n-by-n multiplications; instructions for configuring multiplicand inputs in any of said multiplications to be selectably treatable as signed operands or unsigned operands; instructions for configuring a shifter to shift a second partial product of each of said 2n-by-n multiplications to align it with a first partial product of each of said 2n-by-n multiplications for addition within said third four-multiplier unit; and instructions for configuring circuitry to add results of said multiplications from said first, second and third four-multiplier units. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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Specification