Updating pin locations in a graphical user interface of an electronic design automation tool

• US 9,064,082 B2
• Filed: 10/08/2014
• Issued: 06/23/2015
• Est. Priority Date: 12/27/2012
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Yu, Zhengtao
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US14/509,765
• Publication Number:
  US 20150026656A1
• Time in Patent Office: 258 Days
• Field of Search: 716/139, 716/119, 716/122, 716/124, 716/129, 716/130, 716/131, 716/102, 703/15
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/31 Design entry, e.g. editors specifically adapted for circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/3947 global
• CPC Class Codes: G06F 30/396 Clock trees
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.

Claims

1. In an electronic design automation (EDA) tool, a method for updating pin locations in a graphical user interface (GUI) of the EDA tool, wherein a set of pins are currently located at a set of pin locations on an edge of a block or partition in a circuit design layout, the method comprising:

in a computer when the EDA tool modifies the circuit design layout;

responsive to determining that the edge has increased in length, the EDA tool does not change the set of pin locations in the GUI of the EDA tool;

responsive to determining that the edge has decreased in length but is long enough to preserve the first set of pin locations, the EDA tool does not change the set of pin locations in the GUI of the EDA tool; and

responsive to determining that the edge has decreased in length and is not long enough to preserve the set of pin locations, the EDA tool decreases distances between neighboring signal pins in the GUI of the EDA tool while preserving (1) locations of one or more power pins, (2) relative ordering of signal pins, and (3) locations of one or more fixed pins.

2. The method of claim 1, wherein said decreasing distances between neighboring signal pins includes multiplying each distance by a ratio that is computed by dividing a decreased length of the edge by an original length of the edge.

3. The method of claim 1, wherein said decreasing distances between neighboring signal pins includes snapping one or more pins to wire track locations in the circuit design layout.

4. The method of claim 3, further comprising responsive to determining that two or more pins snapped to the same wire track location, the EDA tool assigns a pin location for each of the two or more pins in a different metal layer.

5. The method of claim 1, further comprising responsive to determining that a portion of the edge is being replaced by two orthogonal edge segments because a corner of the block or partition is being cut in, the EDA tool moves at least one signal pin in the set of pins to one of the two orthogonal edge segments that is parallel to the edge.

6. The method of claim 5, wherein said moving does not preserve relative ordering of signal pins with respect to an edge traversal around the block or partition.

7. The method of claim 1, further comprising responsive to determining that the edge has decreased in length and is not long enough to accommodate a fixed pin location or is not long enough to accommodate the set of pins, the EDA tool alerts a user.

8. The method of claim 1, wherein the pin locations are updated in the GUI of the EDA tool without performing global routing.

9. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for updating pin locations in a graphical user interface (GUI) of an electronic design automation (EDA) tool, wherein a set of pins are currently located at a set of pin locations on an edge of a block or partition in a circuit design layout, the method comprising:

when the EDA tool modifies the circuit design layout;

responsive to determining that the edge has increased in length, the EDA tool does not change the set of pin locations in the GUI of the EDA tool;

responsive to determining that the edge has decreased in length but is long enough to preserve the first set of pin locations, the EDA tool does not change the set of pin locations in the GUI of the EDA tool; and

responsive to determining that the edge has decreased in length and is not long enough to preserve the set of pin locations, the EDA tool decreases distances between neighboring signal pins in the GUI of the EDA tool while preserving (1) locations of one or more power pins, (2) relative ordering of signal pins, and (3) locations of one or more fixed pins.

10. The non-transitory computer-readable storage medium of claim 9, wherein said decreasing distances between neighboring signal pins includes multiplying each distance by a ratio that is computed by dividing a decreased length of the edge by an original length of the edge.

11. The non-transitory computer-readable storage medium of claim 9, wherein said decreasing distances between neighboring signal pins includes snapping one or more pins to wire track locations in the circuit design layout.

12. The non-transitory computer-readable storage medium of claim 11, the method further comprising responsive to determining that two or more pins snapped to the same wire track location, the EDA tool assigns a pin location for each of the two or more pins in a different metal layer.

13. The non-transitory computer-readable storage medium of claim 9, the method further comprising responsive to determining that a portion of the edge is being replaced by two orthogonal edge segments because a corner of the block or partition is being cut in, the EDA tool moves at least one signal pin in the set of pins to one of the two orthogonal edge segments that is parallel to the edge.

14. The non-transitory computer-readable storage medium of claim 13, wherein said moving does not preserve relative ordering of signal pins with respect to an edge traversal around the block or partition.

15. The non-transitory computer-readable storage medium of claim 9, the method further comprising responsive to determining that the edge has decreased in length and is not long enough to accommodate a fixed pin location or is not long enough to accommodate the set of pins, the EDA tool alerts a user.

16. The non-transitory computer-readable storage medium of claim 9, wherein the pin locations are updated in the GUI of the EDA tool without performing global routing.

17. An apparatus, comprising:

a processor; and

non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for updating pin locations in a graphical user interface (GUI) of an electronic design automation (EDA) tool, wherein a set of pins are currently located at a set of pin locations on an edge of a block or partition in a circuit design layout, the method comprising;

when the EDA tool modifies the circuit design layout;

responsive to determining that the edge has increased in length, the EDA tool does not change the set of pin locations in the GUI of the EDA tool;

responsive to determining that the edge has decreased in length but is long enough to preserve the first set of pin locations, the EDA tool does not change the set of pin locations in the GUI of the EDA tool; and

responsive to determining that the edge has decreased in length and is not long enough to preserve the set of pin locations, the EDA tool decreases distances between neighboring signal pins in the GUI of the EDA tool while preserving (1) locations of one or more power pins, (2) relative ordering of signal pins, and (3) locations of one or more fixed pins.

18. The apparatus of claim 17, wherein said decreasing distances between neighboring signal pins includes multiplying each distance by a ratio that is computed by dividing a decreased length of the edge by an original length of the edge.

19. The apparatus of claim 17, wherein said decreasing distances between neighboring signal pins includes snapping one or more pins to wire track locations in the circuit design layout, and wherein the method further comprising responsive to determining that two or more pins snapped to the same wire track location, the EDA tool assigns a pin location for each of the two or more pins in a different metal layer.

20. The apparatus of claim 17, the method further comprising responsive to determining that a portion of the edge is being replaced by two orthogonal edge segments because a corner of the block or partition is being cut in, the EDA tool moves at least one signal pin in the set of pins to one of the two orthogonal edge segments that is parallel to the edge, wherein said moving does not preserve relative ordering of signal pins with respect to an edge traversal around the block or partition.

21. The apparatus of claim 17, the method further comprising responsive to determining that the edge has decreased in length and is not long enough to accommodate a fixed pin location or is not long enough to accommodate the set of pins, the EDA tool alerts a user.

22. The apparatus of claim 17, wherein the pin locations are updated in the GUI of the EDA tool without performing global routing.