Method for adjusting target layout based on intensity of background light in etch mask layer

• US 9,064,085 B2
• Filed: 09/19/2014
• Issued: 06/23/2015
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, Samsung Electronics Co. Ltd.
• Original Assignee: International Business Machines Corporation, Samsung Electronics Co. Ltd.
• Inventors: Chang, Sang Yil, Han, Geng, Li, Wai-kin
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US14/491,241
• Publication Number:
  US 20150007119A1
• Time in Patent Office: 277 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer.

Claims

1. A system for forming a semiconductor circuit, comprising:

a target-layout generator configured to generate target layout data; and

a patterning apparatus configured to receive the target layout data from the target-layout generator,

the patterning apparatus configured to adjust the target layout data based on an intensity of background light that leaks from an exposed region of an etch mask layer to an unexposed region of the etch mask layer,

the patterning apparatus configured to divide the target layout data into a plurality of fragmentations,

the patterning apparatus configured to independently adjust a size of each of the plurality of fragmentations, and

the patterning apparatus configured to pattern a semiconductor substrate based on the adjusted target layout data.

2. The system of claim 1, wherein the target layout data is adjusted by controlling the intensity of the background light to be equal to or lower than a threshold background light intensity.

3. The system of claim 1, wherein the patterning apparatus is configured to produce aerial image information based on the adjusted target layout data.

4. The system of claim 3, wherein the aerial image information includes information on the light leakage.

5. The system of claim 1, wherein the patterning apparatus is configured to perform a simulation based on the adjusted target layout data and the patterning apparatus is configured to determine whether a result of the simulation converges to the target layout data.

6. The system of claim 5, wherein the patterning apparatus is configured to further adjust the adjusted target layout data when the result of the simulation does not converge to the target layout data.

7. The system of claim 1, wherein the patterning apparatus is configured to perform the adjustment of the target layout data a predetermined number of times.

8. The system of claim 1, wherein the patterning apparatus is configured to adjust an edge of the target layout data.

9. The system of claim 1, wherein the patterning apparatus is configured to adjust the intensity of the background light so that the exposed region of the etch mask layer is not removed during an etching process.

10. The system of claim 1, wherein the etch mask layer comprises a photoresist layer.