Memory module having multiple memory banks selectively connectable to a local memory controller and an external memory controller

• US 9,064,562 B2
• Filed: 04/03/2013
• Issued: 06/23/2015
• Est. Priority Date: 04/03/2013
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Venugopal, Raghavan V., Hallowell, William C.
• Primary Examiner(s): GIARDINO JR, MARK A
• Application Number:
  US13/856,013
• Publication Number:
  US 20140304462A1
• Time in Patent Office: 811 Days
• Field of Search: 711/5, 711/115, 711/162, 370/382
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory module includes memory banks, a local memory controller to access data in the memory banks, and an interface to an external memory controller that is configured to access the memory module. Multiplexing circuitry selectively connects the memory banks to the local memory controller and to the interface to the external memory controller.

Claims

1. A memory module comprising:

memory banks;

a local memory controller to access data in the memory banks;

an interface to an external memory controller that is configured to access the memory module; and

multiplexing circuitry to selectively connect the memory banks to the local memory controller and to the interface to the external memory controller, wherein

in a configuration when the multiplexing circuitry connects a first one of the memory banks to the local memory controller, the multiplexing circuitry isolates the first memory bank from the interface to the external memory controller, and

the multiplexing circuitry is to connect, in another configuration, a second one of the memory banks to the interface to the external memory controller while connecting the first memory bank to the local memory controller.

2. The memory module of claim 1, wherein a second one of the memory banks is to respond to a memory request from the external memory controller, wherein the memory request specifies access to data of the first memory bank that is isolated from the external memory controller.

3. The memory module of claim 2, wherein data returned by the second memory bank in response to the memory request for access of the first memory bank is incorrect data from the second memory bank that is not the data requested of the first memory bank in the memory request, and the incorrect data is handled by a host system associated with the external memory controller.

4. The memory module of claim 2, wherein the second memory bank stores a copy of data in the first memory bank, and wherein the data returned by the second memory bank in response to the memory request is from the copy of data.

5. The memory module of claim 1, wherein each of the memory banks includes volatile memory, wherein the memory module further comprises a non-volatile memory, the local memory controller to perform backup of data in at least one of the memory banks to the non-volatile memory.

6. The memory module of claim 1, further comprising control logic to control the multiplexing circuitry to selectively connect the memory banks to the local memory controller and to the interface to the external memory controller.

7. The memory module of claim 6, wherein the control logic is to control the multiplexing circuitry in response to command information from a processor that is external of the memory module.

8. The memory module of claim 6, wherein the control logic is selectively programmable by control information to one of a plurality of modes, the plurality of modes including:

a first mode in which the memory banks are each connected by the multiplexing circuitry to the local memory controller;

a second mode in which one of the memory banks is connected by the multiplexing circuitry to the local memory controller, and another of the memory banks is connected by the multiplexing circuitry to the interface to the external memory controller; and

a third mode in which the memory banks are each connected by the multiplexing circuitry to the interface to the external memory controller.

9. The memory module of claim 1, wherein the local memory controller is to configure an operating speed of the memory banks to an operating speed compatible with whichever one of the local memory controller or the external memory controller the memory banks are selectively connected by the multiplexing circuitry.

10. A method comprising:

configuring a memory module to switch a connection of a first memory bank of multiple memory banks in the memory module from an external interface of the memory module to a local memory controller in the memory module, wherein the external interface is connected to an external memory controller, wherein the configuring includes controlling multiplexing circuitry of the memory module to perform the switch, the multiplexing circuitry to selectively connect the memory banks to the local memory controller and to the interface to the external memory controller; and

in response to a memory request from the external memory controller specifying data in the first memory bank when the first memory bank is connected to the local memory controller and is isolated from the external memory controller by the multiplexing circuitry, providing response data from a second memory bank of the multiple memory banks to the external memory controller.

11. The method of claim 10, further comprising:

during initialization of a host system, configuring the memory module to connect each of the multiple memory banks to the external interface.

12. The method of claim 11, further comprising:

after the initialization of the host system, performing the configuring to switch the first memory bank from the external interface of the memory module to the local memory controller, while the second memory bank is connected to the external interface.

13. The method of claim 10, further comprising:

performing backup of data from the first memory bank to a non-volatile memory in the memory module.

14. The method of claim 13, further comprising:

concurrent with the backup, accessing another of the multiple memory banks by the external memory controller.

15. The method of claim 10, further comprising:

switching the memory module to a shadow mode in which each of the multiple memory banks is connected to the external interface; and

in response to a write request, write a same data to each of the multiple memory banks.

16. The method of claim 10, wherein the configuring includes providing control information from a source external of the memory module to control logic in the memory module.

17. A system comprising:

an external memory controller; and

a memory module connected over a memory bus to the external memory controller, the memory module comprising;

memory banks;

a local memory controller to access data in the memory banks;

an external interface connected to the memory bus; and

multiplexing circuitry to selectively connect the memory banks to the local memory controller and to the external interface,

wherein when the multiplexing circuitry connects a first one of the memory banks to the local memory controller, the multiplexing circuitry isolates the first memory bank from the interface to the external memory controller, and

the multiplexing circuitry is to connect a second one of the memory banks to the external memory controller via the external interface and the memory bus while connecting the first memory bank to the local memory controller.

18. The system of claim 17, wherein the memory module is configurable to connect each of the memory banks to the external interface.

19. The system of claim 17, wherein the external interface is to determine whether the memory bus is idle before the multiplexing circuitry is allowed to switch a connection of the memory bank to the local memory controller.