Semiconductor device and driving method thereof
First Claim
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1. A semiconductor device comprising:
- a volatile memory;
a first transistor;
a second transistor;
a third transistor; and
a first capacitor,wherein a first terminal of the first transistor is electrically connected to the volatile memory,wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor,wherein a first terminal of the second transistor is electrically connected to a first terminal of the third transistor,wherein a second terminal of the third transistor is electrically connected to the volatile memory, andwherein a first terminal of the first capacitor is electrically connected to the gate of the second transistor.
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Abstract
To provide a semiconductor device in which power consumption can be reduced and operation delay due to a stop and a restart of supply of power supply voltage can be suppressed and a driving method thereof. A potential corresponding to data held in a period during which power supply voltage is continuously supplied is saved to a node connected to a capacitor before the supply of power supply voltage is stopped. By utilizing change of channel resistance of a transistor whose gate is the node, data is loaded when the supply of power supply voltage is restarted.
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Citations
18 Claims
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1. A semiconductor device comprising:
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a volatile memory; a first transistor; a second transistor; a third transistor; and a first capacitor, wherein a first terminal of the first transistor is electrically connected to the volatile memory, wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor, wherein a first terminal of the second transistor is electrically connected to a first terminal of the third transistor, wherein a second terminal of the third transistor is electrically connected to the volatile memory, and wherein a first terminal of the first capacitor is electrically connected to the gate of the second transistor. - View Dependent Claims (2, 3, 4)
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5. A semiconductor device comprising:
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a volatile memory; a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a first capacitor; and a second capacitor, wherein a first terminal of the first transistor is electrically connected to the volatile memory, wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor, wherein a first terminal of the second transistor is electrically connected to a first terminal of the third transistor, wherein a second terminal of the third transistor is electrically connected to the volatile memory, wherein a first terminal of the fourth transistor is electrically connected to the volatile memory, wherein a second terminal of the fourth transistor is electrically connected to a gate of the fifth transistor, wherein a first terminal of the fifth transistor is electrically connected to a first terminal of the sixth transistor, wherein a second terminal of the sixth transistor is electrically connected to the volatile memory, wherein a first terminal of the first capacitor is electrically connected to the gate of the second transistor, and wherein a first terminal of the second capacitor is electrically connected to the gate of the fifth transistor. - View Dependent Claims (6, 7, 8)
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9. A method for driving a semiconductor device, the semiconductor device comprising:
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a volatile memory; a first transistor; a second transistor; and a third transistor, wherein a first terminal of the first transistor is electrically connected to the volatile memory, wherein a second terminal of the first transistor is electrically connected to a gate of the second transistor, wherein a first terminal of the second transistor is electrically connected to a first terminal of the third transistor, wherein a second terminal of the third transistor is electrically connected to the volatile memory, and wherein the method for driving the semiconductor device comprises the steps of; supplying a first control signal to a gate of the first transistor to supply charge corresponding to data of the volatile memory to the gate of the second transistor; supplying no power supply voltage to the volatile memory; holding the charge corresponding to the data during the supplying no power supply voltage to the volatile memory; supplying power supply voltage to the volatile memory; and supplying a second control signal to a gate of the third transistor to load the data to the volatile memory. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsAoki, Takeshi, Ikeda, Takayuki, Kurokawa, Yoshiyuki
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Primary Examiner(s)TRAN, MICHAEL THANH
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Application NumberUS14/064,264Publication NumberTime in Patent Office603 DaysField of Search365/149, 365/205US Class Current1/1CPC Class CodesG11C 14/0072 and the nonvolatile element...
