Semiconductor device

• US 9,064,596 B2
• Filed: 02/11/2014
• Issued: 06/23/2015
• Est. Priority Date: 02/12/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Primary Examiner(s): Hiltunen, Thomas J
• Application Number:
  US14/177,501
• Publication Number:
  US 20140226781A1
• Time in Patent Office: 497 Days
• Field of Search: 377/64
• US Class Current: 1/1
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: G11C 29/32 Serial access; Scan testing

Abstract

A register for a scan test has a data saving function. A scan flipflop includes first to third memory circuits. The first memory circuit is a memory circuit functioning as a register of a combination circuit in normal operation. The second memory circuit is a memory circuit for backup of the first memory circuit. The third memory circuit has a function of transferring data to a flipflop in a next stage. Further, the second memory circuit has a function of writing data of the first memory circuit to the third memory circuit and a function of writing data of the third memory circuit to the first memory circuit. At a given time, data of the first memory circuit can be extracted from an external device and data can be stored in the first memory circuit from an external device.

Claims

1. A semiconductor device comprising:

a shift register comprising a plurality of stages, each of the plurality of stages comprising a flipflop,

wherein in each of the plurality of stages, the flipflop comprises a first memory circuit, a second memory circuit and a third memory circuit,

wherein in each of the plurality of stages, the second memory circuit is configured to save data of the first memory circuit, write data of the first memory circuit to the third memory circuit and write data of the third memory circuit to the first memory circuit,

wherein the third memory circuit of each of stages other than a last stage among the plurality of stages is configured to transfer the data to the third memory circuit of a next stage, and

wherein in each of the plurality of stages, each of the second memory circuit and the third memory circuit is configured to hold data in a period during which power supply to the flipflop is stopped.

2. The semiconductor device according to claim 1, further comprising a plurality of combination circuits,

wherein in each of the plurality of stages, the first memory circuit is configured to store data output from a corresponding combination circuit among the plurality of combination circuits.

3. A semiconductor device comprising:

a shift register comprising a first stage and a second stage, each of the first stage and the second stage comprising a flipflop,

wherein in each of the first stage and the second stage, the flipflop comprises a first memory circuit, a second memory circuit and a third memory circuit,

wherein in each of the first stage and the second stage, the first memory circuit comprises a first data holding portion, a first input terminal and a first output terminal,

wherein in each of the first stage and the second stage, the first memory circuit is configured to store data input from the first input terminal to the first data holding portion and output the data stored in the first data holding portion from the first output terminal,

wherein in each of the first stage and the second stage, the third memory circuit comprises a second data holding portion, a second input terminal and a second output terminal,

wherein the second output terminal of the third memory circuit of the first stage is electrically connected to the second input terminal of the third memory circuit of the second stage,

wherein in each of the first stage and the second stage, the third memory circuit is configured to store data input from the second input terminal to the second data holding portion and output the data stored in the second data holding portion from the second output terminal,

wherein in each of the first stage and the second stage, the second memory circuit is configured to store the data stored in the first data holding portion to the second data holding portion and store the data stored in the second data holding portion to the first data holding portion, and

wherein in each of the first stage and the second stage, each of the second memory circuit and the third memory circuit is configured to hold the data in the second data holding portion in a period during which power supply to the flipflop is stopped.

4. The semiconductor device according to claim 3, further comprising a first combination circuit and a second combination circuit,

wherein the first memory circuit of the first stage is configured to store data output from the first combination circuit, and

wherein the second memory circuit of the second stage is configured to store data output from the second combination circuit.

5. The semiconductor device comprising according to claim 3,

wherein in each of the first stage and the second stage, the first data holding portion comprises a first node and a second node,

wherein in each of the first stage and the second stage, the third memory circuit comprises a third node, a fourth node, a switch, a first reading circuit and a second reading circuit,

wherein in each of the first stage and the second stage, the switch is configured to control conduction or non-conduction between the second input terminal and the third node in accordance with a first signal,

wherein in each of the first stage and the second stage, the first reading circuit is configured to read a potential of the third node and output a first potential depending on the potential of the third node to the fourth node in accordance with a second signal,

wherein in each of the first stage and the second stage, the second reading circuit is configured to read a potential of the fourth node and output the first potential depending on the potential of the fourth node to the second output terminal in accordance with the potential of the fourth node,

wherein in each of the first stage and the second stage, the second memory circuit comprises a third reading circuit, a fourth reading circuit, a fifth reading circuit and a sixth reading circuit,

wherein in each of the first stage and the second stage, the third reading circuit is configured to read a potential of the first node and output the first potential depending on the potential of the first node to the third node in accordance with a third signal,

wherein in each of the first stage and the second stage, the fourth reading circuit is configured to read a potential of the second node and output the first potential depending on the potential of the second node to the fourth node in accordance with the third signal,

wherein in each of the first stage and the second stage, the fifth reading circuit is configured to read the potential of the third node and output the first potential depending on the potential of the third node to the first node in accordance with a fourth signal, and

wherein in each of the first stage and the second stage, the sixth reading circuit is configured to read the potential of the fourth node and output the first potential depending on the potential of the fourth node to the second node in accordance with the fourth signal.

6. The semiconductor device according to claim 5,

wherein in each of the first stage and the second stage, the switch comprises a first transistor,

wherein in each of the first stage and the second stage, the first signal is input to a gate of the first transistor,

wherein in each of the first stage and the second stage, one of a source and a drain of the first transistor is connected to the second input terminal,

wherein in each of the first stage and the second stage, the other of the source and the drain of the first transistor is connected to the third node,

wherein in each of the first stage and the second stage, the first reading circuit comprises a second transistor and a third transistor connected in series between a first wiring to which the first potential is supplied and the fourth node,

wherein in each of the first stage and the second stage, a gate of the second transistor is connected to the third node,

wherein in each of the first stage and the second stage, the second signal is input to a gate of the third transistor,

wherein in each of the first stage and the second stage, the second reading circuit comprises a fourth transistor,

wherein in each of the first stage and the second stage, a gate of the fourth transistor is connected to the fourth node,

wherein in each of the first stage and the second stage, one of a source and a drain of the fourth transistor is connected to a second wiring to which the first potential is supplied, and

wherein in each of the first stage and the second stage, the other of the source and the drain of the fourth transistor is connected to the second output terminal.

7. The semiconductor device according to claim 6,

wherein in each of the first stage and the second stage, each of the first transistor, the second transistor, the third transistor and the fourth transistor comprises a channel formation region in an oxide semiconductor layer.

8. The semiconductor device according to claims 5,

wherein in each of the first stage and the second stage, the third reading circuit comprises a fifth transistor and a sixth transistor connected in series,

wherein in each of the first stage and the second stage, a gate of the fifth transistor is connected to the first node,

wherein in each of the first stage and the second stage, one of a source and a drain of the fifth transistor is connected to a third wiring to which the first potential is supplied,

wherein in each of the first stage and the second stage, the third signal is input to a gate of the sixth transistor,

wherein in each of the first stage and the second stage, one of a source and a drain of the sixth transistor is connected to the third node,

wherein in each of the first stage and the second stage, the fourth reading circuit comprises a seventh transistor and an eighth transistor connected in series,

wherein in each of the first stage and the second stage, a gate of the seventh transistor is connected to the second node,

wherein in each of the first stage and the second stage, one of a source and a drain of the seventh transistor is connected to a fourth wiring to which the first potential is supplied,

wherein in each of the first stage and the second stage, the third signal is input to a gate of the eighth transistor, and

wherein in each of the first stage and the second stage, one of a source and a drain of the eighth transistor is connected to the fourth node.

9. The semiconductor device according to claim 8,

wherein in each of the first stage and the second stage, at least one of the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor comprises a channel in an oxide semiconductor layer.

10. The semiconductor device according to claim 5,

wherein in each of the first stage and the second stage, the fifth reading circuit comprises a ninth transistor and a tenth transistor connected in series,

wherein in each of the first stage and the second stage, a gate of the ninth transistor is connected to the third node,

wherein in each of the first stage and the second stage, one of a source and a drain of the ninth transistor is connected to a fifth wiring to which the first potential is supplied,

wherein in each of the first stage and the second stage, the fourth signal is input to a gate of the tenth transistor,

wherein in each of the first stage and the second stage, one of a source and a drain of the tenth transistor is connected to the first node,

wherein in each of the first stage and the second stage, the sixth reading circuit comprises an eleventh transistor and a twelfth transistor connected in series,

wherein in each of the first stage and the second stage, a gate of the eleventh transistor is connected to the fourth node,

wherein in each of the first stage and the second stage, one of a source and a drain of the eleventh transistor is connected to the fifth wiring to which the first potential is supplied,

wherein in each of the first stage and the second stage, the fourth signal is input to a gate of the twelfth transistor, and

wherein in each of the first stage and the second stage, one of a source and a drain of the twelfth transistor is connected to the second node.

11. The semiconductor device according to claim 5, further comprising a thirteenth transistor and a fourteenth transistor,

wherein in each of the first stage and the second stage, one of a source and a drain of the thirteenth transistor is connected to the third node,

wherein in each of the first stage and the second stage, the other of the source and the drain of the thirteenth transistor is connected to a sixth wiring to which a second potential is supplied,

wherein in each of the first stage and the second stage, one of a source and a drain of the fourteenth transistor is connected to the fourth node, and

wherein in each of the first stage and the second stage, the other of the source and the drain of the fourteenth transistor is connected to a seventh wiring to which the second potential is supplied.

12. A semiconductor device comprising:

a shift register comprising a first stage and a second stage, each of the first stage and the second stage comprising;

a first data holding portion comprising;

a first node; and

a second node;

a second data holding portion comprising;

a third node; and

a fourth node;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor; and

a sixth transistor,

wherein in each of the first stage and the second stage, a gate of the first transistor is connected to the first node,

wherein in each of the first stage and the second stage, a gate of the second transistor is connected to the second node,

wherein in each of the first stage and the second stage, one of a source and a drain of the first transistor is connected to the third node,

wherein in each of the first stage and the second stage, one of a source and a drain of the second transistor is connected to the fourth node,

wherein in each of the first stage and the second stage, one of a source and a drain of the third transistor is connected to the first node,

wherein in each of the first stage and the second stage, one of a source and a drain of the fourth transistor is connected to the second node,

wherein in each of the first stage and the second stage, a gate of the third transistor is connected to the third node,

wherein in each of the first stage and the second stage, a gate of the fourth transistor is connected to the fourth node,

wherein in each of the first stage and the second stage, a gate of the fifth transistor is connected to the third node,

wherein in each of the first stage and the second stage, one of a source and a drain of the fifth transistor is connected to the fourth node,

wherein in each of the first stage and the second stage, a gate of the sixth transistor is connected to the fourth node, and

wherein one of a source and a drain of the sixth transistor of the first stage is connected to the third node of the second stage.

13. The semiconductor device according to claim 12, further comprising a first combination circuit and a second combination circuit,

wherein the first data holding portion of the first stage is configured to store data output from the first combination circuit, and

wherein the first data holding portion of the second stage is configured to store data output from the second combination circuit.

14. The semiconductor device according to claim 12, further comprising a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor,

wherein in each of the first stage and the second stage, the one of the source and the drain of the first transistor is connected to the third node via the seventh transistor,

wherein in each of the first stage and the second stage, the one of the source and the drain of the second transistor is connected to the fourth node via the eighth transistor,

wherein in each of the first stage and the second stage, the one of the source and the drain of the third transistor is connected to the first node via the ninth transistor,

wherein in each of the first stage and the second stage, the one of the source and the drain of the fourth transistor is connected to the second node via the tenth transistor,

wherein in each of the first stage and the second stage, one of a source and a drain of the eleventh transistor is connected to the third node,

wherein in each of the first stage and the second stage, the one of the source and the drain of the fifth transistor is connected to the fourth node via the twelfth transistor, and

wherein the one of the source and the drain of the sixth transistor of the first stage is connected to the third node of the second stage via the eleventh transistor of the second stage.

15. The semiconductor device according to claim 14,

wherein in each of the first stage and the second stage, each of the fifth transistor, the sixth transistor, the eleventh transistor and the twelfth transistor comprises a channel formation region in an oxide semiconductor layer.

16. The semiconductor device according to claim 14,

wherein in each of the first stage and the second stage, at least one of the first transistor, the second transistor, the seventh transistor and the eighth transistor comprises a channel in an oxide semiconductor layer.

17. The semiconductor device according to claim 14, further comprising a thirteenth transistor and a fourteenth transistor,

wherein in each of the first stage and the second stage, one of a source and a drain of the thirteenth transistor is connected to the third node, and

wherein in each of the first stage and the second stage, one of a source and a drain of the fourteenth transistor is connected to the fourth node.