Monolithic microwave integrated circuit
First Claim
1. A monolithic microwave integrated circuit, comprising:
- a semiconductor substrate having a bulk resistivity equal to or greater than about 100 Ohm-cm, and having a front surface and a rear surface;
at least one transistor in the semiconductor substrate and having an input terminal, an output terminal, a reference terminal, and a source region;
a dielectric layer formed over the front surface and overlying the source region;
at least one capacitor monolithically formed over the semiconductor substrate;
at least one inductor monolithically formed over the semiconductor substrate;
planar interconnections overlying the semiconductor substrate coupling the at least one transistor, capacitor, and inductor to form the monolithic integrated circuit;
a first conductive through-substrate via (TSV) extending through the dielectric layer and through the semiconductor substrate; and
an interlayer via formed in the first dielectric layer, the first conductive TSV electrically coupled to the source region of the transistor through the interlayer via.
31 Assignments
0 Petitions
Accused Products
Abstract
Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44′, 45′) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1′, 52-1′, 94, 94′, 94″) overlying the substrate (60). The active transistor(s) (41′) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42′, 43′) are also formed over the front face (63) of the substrate (60). Various terminals (42-1′, 42-2′, 43-1, 43-2′,50′, 51′, 52′, 42-1′, 42-2′, etc.) of the transistor(s) (41′), capacitor(s) (42′, 43′) and inductor(s) (44′, 45′) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (44′, 45′) and heavy current carrying conductors (52-1′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC (46, 58) previously unobtainable.
78 Citations
20 Claims
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1. A monolithic microwave integrated circuit, comprising:
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a semiconductor substrate having a bulk resistivity equal to or greater than about 100 Ohm-cm, and having a front surface and a rear surface; at least one transistor in the semiconductor substrate and having an input terminal, an output terminal, a reference terminal, and a source region; a dielectric layer formed over the front surface and overlying the source region; at least one capacitor monolithically formed over the semiconductor substrate; at least one inductor monolithically formed over the semiconductor substrate; planar interconnections overlying the semiconductor substrate coupling the at least one transistor, capacitor, and inductor to form the monolithic integrated circuit; a first conductive through-substrate via (TSV) extending through the dielectric layer and through the semiconductor substrate; and an interlayer via formed in the first dielectric layer, the first conductive TSV electrically coupled to the source region of the transistor through the interlayer via. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A monolithic microwave integrated circuit having a circuit input terminal, a circuit output terminal and a circuit reference terminal, comprising:
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a semiconductor substrate having a bulk resistivity equal to or greater than about 100 Ohm-cm, and having a front surface and a rear surface, wherein the rear surface has thereon the circuit reference terminal; at least one Laterally-Diffused-Metal-Oxide-Semiconductor (LDMOS) transistor formed in the substrate and having a transistor input terminal, a transistor output terminal, a transistor reference terminal, a source region, and a body contact region laterally adjacent the source region, wherein the transistor reference terminal is coupled to the circuit reference terminal; a first dielectric layer formed over the front surface; at least first and second monolithic planar capacitors overlying the front surface; at least first and second monolithic planar inductors overlying the front surface; and at least one conductive through-substrate via electrically coupled to the source region and formed through the semiconductor substrate, through the body contact region of the at least one LDMOS transistor and through a region of the first dielectric layer overlying the body contact region; wherein the first capacitor is coupled between the circuit input terminal and the circuit reference terminal, and the first inductor is coupled between the circuit input terminal and the transistor input terminal; and wherein the second capacitor and the second inductor are coupled in series to form a combination, and a first terminal of the combination is coupled to the transistor output terminal and to the circuit output terminal and a second terminal of the combination is coupled to the circuit reference terminal. - View Dependent Claims (10, 11, 12)
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13. A monolithic microwave integrated circuit, comprising:
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a semiconductor substrate having a front surface and a rear surface; a transistor formed in the semiconductor substrate and including a source region; an inductor monolithically formed over the semiconductor substrate; planar interconnections overlying the front surface of the semiconductor substrate and coupling the transistor and inductor; a reference node supported by the rear surface of the semiconductor substrate; a first dielectric layer formed over the semiconductor substrate; a first through-substrate via (“
TSV”
) extending through the first dielectric layer and the substrate to electrically couple the transistor to the reference node; andan interlayer via formed in the first dielectric layer, the first TSV electrically coupled to the source region of the transistor through the interlayer via; wherein the region of the semiconductor substrate through which the first TSV passes has a bulk resistivity equal to or greater than about 1000 Ohm-cm; and wherein at least a portion of the inductor is formed over a region of the semiconductor substrate located adjacent the first TSV. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification