Stacking devices at finished package level

• US 9,064,716 B2
• Filed: 09/30/2009
• Issued: 06/23/2015
• Est. Priority Date: 09/30/2009
• Status: Active Grant

• Current Assignee: Virtium LLC
• Original Assignee: Virtium Technology
• Inventors: Hoang, Phan, Nguyen, Chinh Minh
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US12/571,313
• Publication Number:
  US 20110074002A1
• Time in Patent Office: 2,092 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 of a flip chip
• CPC Class Codes: H01L 2924/19107 off-chip wires

Abstract

An embodiment is a method and apparatus to stack devices. A first finished package level (FPL) device having a first grounded tested die (GTD) is reduced to nearly size of the first GTD. The first FPL has a first plurality of solder balls. The reduced first FPL device is attached to a first substrate to form a first device assembly.

Claims

1. A method comprising:

reducing a first finished package level (FPL) device having a first grounded tested die (GTD) to nearly size of the first GTD, the first FPL having a first plurality of solder balls; and

attaching the reduced first FPL device to a first substrate to form a first device assembly,

wherein the first FPL being a device that is previously tested and packaged by an IC manufacturer.

2. The method of claim 1 wherein reducing comprises:

grinding left and right sides of the first FPL device to nearly the size of the first GTD; and

grinding top surface of the first FPL device.

3. The method of claim 1 wherein attaching comprises:

applying a solder paste to the first substrate; and

reflowing the solder paste.

4. The method of claim 3 wherein attaching further comprises:

seating the reduced first FPL device into the first substrate having clearing holes that fit the first plurality of solder balls such that the solder balls are inserted into the clearing holes.

5. The method of claim 1 further comprising:

reducing a second FPL device having a second GTD to nearly size of the second GTD, the second FPL having a second plurality of solder balls;

attaching the reduced second FPL device to a second substrate to form a second device assembly; and

stacking the second device assembly on top of the first device assembly.

6. The method of claim 5 wherein stacking comprises:

attaching the second substrate to the reduced first FPL device.

7. The method of claim 5 further comprising:

wire bonding the second substrate to the first substrate; and

encapsulating the second device assembly and the first device assembly.

8. The method of claim 1 wherein attaching the reduced first FPL device to the first substrate comprises:

stepping the first substrate to a predetermined thickness, the stepped first substrate having a cavity; and

attaching the reduced first FPL device to top surface of the stepped first substrate.

9. The method of claim 8 further comprising:

reducing a second FPL device having a second GTD to nearly size of the second GTD, the second FPL having a second plurality of solder balls;

attaching the reduced second FPL device to bottom surface of the stepped first substrate into the cavity; and

encapsulating the reduced first FPL device.

10. The method of claim 1 wherein the first FPL device is a ball grid array (BGA) device.