Semiconductor structure having metal gate and manufacturing method thereof

• US 9,064,814 B2
• Filed: 06/19/2013
• Issued: 06/23/2015
• Est. Priority Date: 06/19/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Wu, Yi-Ching, Huang, Chih-Sen, Hung, Ching-Wen
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US13/921,221
• Publication Number:
  US 20140374805A1
• Time in Patent Office: 734 Days
• Field of Search: 257/369, 257/371, 257/412
• US Class Current: 1/1
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A manufacturing method for a semiconductor device first provides a substrate having at least a first transistor formed thereon. The first transistor includes a first conductivity type. The first transistor further includes a first metal gate and a protecting layer covering sidewalls of the first metal gate. A portion of the first metal gate is removed to form a first recess and followed by removing a portion of the protecting layer to form a second recess. Then, an etch stop layer is formed in the second recess.

Claims

1. A semiconductor device comprising:

a substrate;

a transistor formed on the substrate, the transistor comprising a metal gate;

an etch stop layer formed on a top of the metal gate, a width of the etch stop layer being larger than a width of the metal gate; and

an interlayer dielectric (ILD) layer surrounding the transistor, a top of the etch stop layer and a top of the ILD layer being coplanar.

2. The semiconductor device according to claim 1, further comprising a protecting layer covering sidewalls of the metal gate.

3. The semiconductor device according to claim 2, wherein the protecting layer comprises at least a spacer.

4. The semiconductor device according to claim 3, wherein the protecting layer further comprises a contact etch stop layer (CESL).

5. The semiconductor device according to claim 2, wherein a bottom of the etch stop layer contacts a top of the protecting layer.

6. The semiconductor device according to claim 1, wherein a thickness of the etch stop layer is between 250 Å

and 400 Å

.

7. The semiconductor device according to claim 1, further comprising at least a contact plug formed in the ILD layer.