Insulated gate bipolar transistors including current suppressing layers

• US 9,064,840 B2
• Filed: 08/22/2014
• Issued: 06/23/2015
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Zhang, Qingchun
• Primary Examiner(s): Niesz, Jamie C
• Application Number:
  US14/465,931
• Publication Number:
  US 20140363931A1
• Time in Patent Office: 305 Days
• Field of Search: 438/135
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region.

Claims

1. A method of forming a transistor, comprising:

providing a substrate having a first conductivity type;

forming a drift layer on the substrate, wherein the drift layer has a second conductivity type opposite the first conductivity type;

forming a current suppressing layer on the drift layer, wherein the current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer;

forming a well region in the current suppressing layer, wherein the well region has the first conductivity type; and

forming an emitter region in the well region, wherein the emitter region has the second conductivity type,

wherein the current suppressing layer has a thickness and doping concentration that reduce current gain of a bipolar transistor portion of the transistor formed by the well region, the drift layer and the substrate, and thereby enhance carrier accumulation in a channel region of the transistor.

2. The method of claim 1, wherein forming the current suppressing layer comprises growing an epitaxial layer on the drift layer.

3. The method of claim 2, wherein the substrate comprises an off-axis n-type silicon carbide substrate, wherein forming the drift layer comprises forming a p-type silicon carbide epitaxial layer on the substrate, and wherein forming the current suppressing layer comprises forming a p-type silicon carbide epitaxial layer on the drift layer.

4. The method of claim 1, wherein the current suppressing layer has a thickness of about 1 μ

m.

5. The method of claim 1, wherein the current suppressing layer has a doping concentration of about 1×

10¹⁵ cm<sup>−

3</sup> to about 1×

10¹⁷ cm<sup>−

3</sup>.

6. The method of claim 4, wherein the current suppressing layer has a doping concentration of about 1×

10¹⁶ cm<sup>−

3</sup>.

7. The method of claim 1, wherein forming the well region comprises forming the well region to have a junction depth that is less than a thickness of the current suppressing layer.

8. The method of claim 1,

wherein the current suppressing layer has a thickness of about 1 μ

m, and

wherein the well region has a junction depth of about 0.5 μ

m.

9. The method of claim 1, wherein the transistor comprises an insulated gate bipolar transistor.

10. A method of forming a transistor, comprising:

providing an n-type silicon carbide substrate;

forming a p-type silicon carbide drift layer on the n-type silicon carbide substrate;

forming a p-type epitaxial silicon carbide current suppressing layer on the p-type silicon carbide drift layer, the epitaxial current suppressing layer having a doping concentration that is larger than a doping concentration of the p-type silicon carbide drift layer;

forming a first n+ well region in the epitaxial current suppressing layer, wherein the first n+ well region has a junction depth that is less than a thickness of the epitaxial current suppressing layer; and

forming a p+ emitter region in the first n+ well region,

wherein the epitaxial current suppressing layer has a thickness and doping concentration that reduce current gain of a bipolar transistor portion of the transistor formed by the first n+ well region, the p-type silicon carbide drift layer and the n-type silicon carbide substrate, and thereby enhance hole accumulation in a channel region of the transistor.

11. The method of claim 10, further comprising:

forming a second n+ well region in the epitaxial current suppressing layer, wherein the second n+ well region has a junction depth that is less than a thickness of the epitaxial current suppressing layer, and wherein the first and second n+ well regions are separated by the current suppressing layer; and

forming a JFET region in between the first and second n+ well regions.

12. The method of claim 11, wherein p-type dopants in the JFET region are formed to have a doping concentration of about 1×

10¹⁶ cm<sup>−

3</sup>.

13. The method of claim 11, further comprising:

forming a buried channel region in the first n+ well region between the p+ emitter region and the JFET region.

14. The method of claim 13, wherein forming the buried channel region modifies a threshold voltage and/or an inversion channel mobility of the insulated gate bipolar transistor.

15. The method of claim 13, wherein forming the buried channel region comprises implanting p-type dopants into the first n+ well region.

16. The method of claim 10, wherein the transistor comprises an insulated gate bipolar transistor.