Transistor structure with feed-through source-to-substrate contact

• US 9,064,896 B2
• Filed: 12/10/2013
• Issued: 06/23/2015
• Est. Priority Date: 11/02/2009
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Terrill, Kyle
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US14/102,208
• Publication Number:
  US 20140099765A1
• Time in Patent Office: 560 Days
• Field of Search: 257/271, 257/288, 257/327, 257/341, 438/218, 438/570
• US Class Current: 1/1
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer.

Claims

1. A method of fabricating a semiconductor device, said method comprising:

forming a source region and a drain region in an epitaxial layer grown over a substrate layer;

forming a gate shield that extends over said source region and drain region;

forming a trench-like feed-through element that is filled with metal and passes through said epitaxial layer and that is in contact with said substrate layer and said source region, wherein an upper portion of said feed-through element is wider than a lower portion of said feed-through element, forming a ledge where said upper portion and said lower portion meet, wherein said gate shield contacts said feed- through element at said ledge;

forming a drain contact over said drain region; and

forming a first oxide layer over the surface of said metal in said feed-through element and a doped glass layer over said first oxide layer.

2. The method of claim 1 further comprising forming a barrier layer over said doped glass layer, wherein said barrier layer also extends into and lines a trench containing said drain contact and separates said drain contact from said first oxide layer and said doped glass layer.

3. The method of claim 1 wherein said gate shield is formed over said source region, wherein a portion of said gate shield that is over said source region is in contact with said source region.

4. The method of claim 1 wherein said gate shield comprises polysilicon.

5. The method of claim 1 wherein said metal comprises tungsten.

6. The method of claim 1, prior to forming said first oxide layer and said doped glass layer further comprising:

depositing a second oxide layer over said gate shield and said source region;

performing a first etch through said second oxide layer and to said epitaxial layer to form a trench corresponding to said upper portion of said feed-through element; and

performing a second etch to extend said trench through said epitaxial layer and into said substrate layer to form said lower portion of said feed-through element.

7. The method of claim 6 further comprising, after said second etch, coating said trench with a barrier layer and filling said trench with said metal.

8. The method of claim 7 wherein said barrier layer comprises titanium nitride.

10. The method of claim 1 wherein said device is selected from the group consisting of:

a flip chip; and

a laterally diffused metal oxide semiconductor (LDMOS) device.

17. The method of claim 1 wherein said gate shield comprises polysilicon.

9. A method of fabricating a semiconductor device, said method comprising:

forming a source region and a drain region, both of a second conductivity type, in an epitaxial layer grown over a heavily doped substrate layer, both of a first conductivity type;

forming a drain contact, wherein said epitaxial and substrate layers are isolated from said drain contact by a reversed-bias junction and a MOSFET (metal oxide semiconductor field effect transistor) channel;

forming an electrically conductive trench-like feed-through element that is filled with metal and passes through said epitaxial layer and in contact with said substrate layer and said source region;

forming a gate shield in contact with said feed-through element and over said source region, wherein an upper portion of said feed-through element is wider than a lower portion of said feed-through element;

forming a ledge, where said upper portion and said lower portion meet, and said gate shield contacts said feed-through element at said ledge; and

forming an oxide layer over the surface of said metal in said feed-through element and a doped glass layer over said oxide layer.

11. The method of claim 9 wherein said metal comprises tungsten.

12. The method of claim 9 further comprising forming a barrier layer over said doped glass layer.

13. The method of claim 12 wherein said barrier layer also extends into and lines a trench containing said drain contact and separates said drain contact from said oxide layer and said doped glass layer.

14. The method of claim 9 wherein said forming said feed-through element comprises:

forming a trench in said epitaxial layer and extending into said substrate layer;

coating said trench with a barrier layer; and

filling said trench with said metal.

15. The method of claim 14 wherein said barrier layer comprises titanium nitride.

16. The method of claim 9 wherein said gate shield comprises a portion that is above and extends over said source region, wherein said portion that is above and over said source region is in contact with said source region.