Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors

• US 9,064,903 B2
• Filed: 02/04/2014
• Issued: 06/23/2015
• Est. Priority Date: 02/28/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Mitchell, Allan T., Khan, Imran Mahmood, Wu, Michael A.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): SKYLES, TIFNEY L
• Application Number:
  US14/172,608
• Publication Number:
  US 20140154850A1
• Time in Patent Office: 504 Days
• Field of Search: 257/296, 438/238, 438/239
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Claims

1. A method of fabricating an electrically programmable capacitor structure for an analog semiconductor integrated circuit, formed at a semiconductor surface of a body, comprising the steps of:

forming isolation dielectric structures at selected locations of the semiconductor surface, the isolation dielectric structures defining active regions of the surface therebetween;

forming a gate dielectric layer over the active regions;

then forming an electrode layer comprised of polycrystalline silicon overall;

removing selected portions of the electrode layer to define a first electrode comprised of polycrystalline silicon;

the first electrode including a portion overlying an isolation dielectric structure and a plurality of portions overlying active regions;

doping the polycrystalline silicon to a first conductivity type;

performing an ion implantation of dopant of a second conductivity type, opposite to the first conductivity type, into a first active region to define a buried transistor channel;

forming source and drain regions of the second conductivity type on opposite sides of a portion of the first electrode overlying the first active region;

then depositing a dielectric film overall;

then depositing a conductor layer comprising a metal; and

removing selected portions of the conductor layer to define a first conductive plate overlying the dielectric film and a portion of the first electrode, at a location overlying an isolation dielectric structure.

2. The method of claim 1, wherein the step of removing selected portions of the electrode layer also defines a second electrode of polycrystalline silicon;

wherein the method further comprises;

forming a layer of silicon dioxide over the first and second electrodes;

removing the silicon dioxide selectively from the second electrode and from an opening at the first location of the first electrode, so that the silicon dioxide remains over the first electrode at locations other than the first location;

after the step of removing the silicon dioxide, reacting exposed portions of the polycrystalline silicon, including the second electrode and at the first location of the first electrode, with a metal to form a metal silicide.

3. The method of claim 2, wherein the step of removing selected portions of the conductor layer also defines a second conductive plate overlying the dielectric film and a portion of the second electrode, at a location overlying an isolation dielectric structure.

4. The method of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

5. The method of claim 4, wherein the first electrode overlies second and third active regions;

wherein the step of forming source and drain regions forms n-type source and drain regions on opposite sides of the first electrode overlying the second active region;

and wherein the step of forming source and drain regions forms p-type source and drain regions on opposite sides of the first electrode overlying the third active region.