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Power semiconductor device

  • US 9,064,925 B2
  • Filed: 09/24/2012
  • Issued: 06/23/2015
  • Est. Priority Date: 03/23/2010
  • Status: Active Grant
First Claim
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1. A power semiconductor, comprising:

  • a drift layer of a first conductivity type arranged between an emitter electrode on an emitter side and a collector electrode on a collector side of the device;

    a first base layer of a second conductivity type arranged between the drift layer and the emitter electrode, which first base layer is in direct electrical contact to the emitter electrode;

    a first source region of the first conductivity type arranged at the emitter side embedded into the first base layer in contact with the emitter electrode, which first source region has a higher doping concentration than the drift layer;

    a plurality of first gate electrodes, each electrically insulated from the first base layer, the first source region and the drift layer by a first insulating layer, which first gate electrode is arranged in a same plane and lateral to the first base layer and extends deeper into the drift layer than the first base layer, a channel being formable between the emitter electrode, the first source region, the first base layer and the drift layer; and

    a second base layer of the second conductivity type, a second source region of the first conductivity type and a second gate electrode, wherein;

    the second gate electrode is arranged outside an area between the emitter side and the collector side, the second gate electrode is electrically insulated from the second base layer, the second source region and the drift layer by a second insulating layer;

    wherein;

    the second source region is arranged at the emitter side embedded into the second base layer and extends into a region past the second gate electrode, which second source region has a higher doping concentration than the drift layer;

    wherein;

    the second base layer is arranged in a same plane and lateral to the first base layer; and

    wherein the first and second source regions are connected to each other by a connection source region, which is arranged between two such first gate electrodes and thereby separates said two first gate electrodes.

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