Through-silicon via with low-K dielectric liner

• US 9,064,940 B2
• Filed: 01/02/2013
• Issued: 06/23/2015
• Est. Priority Date: 01/13/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US13/732,622
• Publication Number:
  US 20130119521A1
• Time in Patent Office: 902 Days
• Field of Search: 257/774, 257/686, 257/737, 257/738, 257/621, 438/667
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/059 : Being combinations of any of the materials from the groups H01L2924/042 - H01L2924/0584, e.g. oxynitrides
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.

Claims

1. A device comprising:

a substrate having a circuit side and a backside opposite the circuit side;

a through via extending through the substrate;

a second dielectric layer disposed on the circuit side of the substrate; and

a first dielectric layer interposed between the through via and the substrate, the first dielectric layer extending over at least a portion of a surface of the backside of the substrate, and at least a portion of the first dielectric layer extending over at least a portion of the circuit side of the substrate and through the substrate to the backside of the substrate, the first dielectric layer disposed on the circuit side of the substrate between the second dielectric layer and a conductive element;

wherein the conductive element extends from the via to a contact disposed on the second dielectric layer.

2. The device of claim 1, wherein the first dielectric layer has a dielectric constant less than about 3.5.

3. The device of claim 1, wherein a portion of the through via protrudes from the backside of the substrate.

4. The device of claim 1, wherein the first dielectric layer extends over a portion of the contact.

5. The device of claim 1, wherein a portion of the through via protrudes from the first dielectric layer.

6. The device of claim 5, wherein the through via extends from the backside of the substrate above an uppermost portion of the first dielectric layer disposed on the backside of the substrate.

7. A device comprising:

a substrate having a circuit side and a backside opposite the circuit side;

a through via disposed in an opening in the substrate, the through via extending through the substrate;

a first contact disposed over the circuit side of the substrate and spaced apart from the opening in the substrate;

a conductive element disposed on the circuit side of the substrate and in contact with a portion of the through via extending over the circuit of the substrate, the conductive element in contact with the first contact; and

a first dielectric layer interposed between the through via and the substrate, the first dielectric layer disposed over at least a portion of a surface of the backside of the substrate, the first dielectric layer extending from the backside of the substrate through the opening and over a second dielectric layer formed on the circuit side of the substrate, at least a portion of the first dielectric layer disposed between the substrate and the conductive element on the circuit side of the substrate in a region between the opening and the contact;

wherein the first contact is disposed on the second dielectric layer and wherein a portion of the second dielectric layer is disposed between the substrate and the conductive element.

8. The device of claim 7, wherein the first dielectric layer extends over a portion of a top surface of the first contact.

9. The device of claim 7, wherein the conductive element is in contact with the through via, and the conductive element is spaced apart from the substrate.

10. The device of claim 7, wherein the first dielectric layer comprises a material having a dielectric constant less than about 3.5.

11. The device of claim 7, wherein the first dielectric layer has a dielectric constant greater than about 3.5.

12. The device of claim 7, wherein the first dielectric layer comprises polyimide.

13. The device of claim 7, wherein the through via protrudes from the backside of the substrate.

14. The device of claim 13, wherein the through via extends from the backside above the first dielectric layer disposed on the backside of the substrate.

15. A method of forming a semiconductor device, the method comprising:

providing a substrate having a through via extending from a circuit side partially through the substrate, the substrate having one or more dielectric layers disposed over the circuit side of the substrate and a conductive line formed over the one or more dielectric layers, a first liner being interposed between the through via and the substrate and extending between the one or more dielectric layers and the conductive line;

thinning a backside of the substrate such that at least a portion of the first liner is exposed;

removing at least a portion of the first liner interposed between the through via and the substrate, thereby forming an opening around the through via on the backside of the substrate and extending to the circuit side of the substrate and over the circuit side of the substrate and between the one or more dielectric layers and conductive line, the opening having a uniform width between the through via and the substrate; and

forming a second liner in the opening.

16. The method of claim 15, wherein the second liner extends over a portion of the backside of the substrate.

17. The method of claim 15, wherein the second liner comprises a dielectric material having a lower dielectric constant than the first liner.

18. The method of claim 15, wherein the second liner extends over at least a portion of the circuit side of the substrate.

19. The method of claim 15, wherein the second liner is formed of an extra low-k dielectric.

20. The method of claim 15, wherein the conductive line extends from the via to a contact disposed on one of the one or more dielectric layers.