Island matrixed gallium nitride microwave and power switching transistors

• US 9,064,947 B2
• Filed: 08/04/2010
• Issued: 06/23/2015
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Original Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Inventors: Roberts, John, Mizan, Ahmad, Patterson, Girvan, Klowak, Greg
• Primary Examiner(s): Au, Bac
• Assistant Examiner(s): NGUYEN, SOPHIA T
• Application Number:
  US13/388,694
• Publication Number:
  US 20120138950A1
• Time in Patent Office: 1,784 Days
• Field of Search: 257/194, 257/76, 257/280, 257/613, 257/615, 257/192, 438/22
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.

Claims

1. A nitride semiconductor device comprising:

a) a substrate;

b) a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate;

c) a plurality of source island electrodes and a plurality of drain island electrodes of a multi-island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and arranged with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer, with;

i) at least one side of each of the source island electrodes opposite a side of an adjacent drain island electrode;

ii) at least one side of each of the drain island electrodes opposite a side of an adjacent source island electrode;

d) a plurality of gate electrodes formed on the nitride semiconductor layer in active regions between each of the source island electrodes and each of the drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes;

and

e) each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a bump or ball connection formed thereon;

f) each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump or ball connection formed thereon;

and

g) the low resistance gate interconnect being connected to a plurality of gate pads.

2. The device of claim 1, wherein the drain and source island electrodes are each a four-sided figure.

3. The device of claim 1, wherein the drain and source island electrodes are triangular shaped.

4. The device of claim 1, wherein the drain and source island electrodes are a combination of various variants of polygon shapes that allow drain/source island juxtapositioning.

5. The device of claim 1, wherein the low resistance gate interconnect comprises a low resistance metal strap connecting each of the plurality of gate electrodes to the plurality of gate pads.

6. The device of claim 1, further comprising one or more epitaxial layers in between said substrate and said nitride semiconductor layer.

7. The device of claim 6, wherein said one or more epitaxial layers are lightly doped.

8. The device of claim 6, further comprising a plurality of epitaxial layers and one or more field plates, wherein each said field plate is positioned between successive epitaxial layers.

9. The device of claim 1, wherein each of the said first and second ball connections is formed of gold.

10. The device of claim 1 wherein the nitride semiconductor layer is a hetero layer consisting of a layer of undoped gallium nitride beneath a layer of undoped aluminum gallium nitride.

11. The device of claim 1, wherein each of the gate electrodes is formed from palladium, and source and drain island electrodes are made from titanium and aluminum.

12. The device of claim 1, wherein the substrate is an insulative high resistance substrate, and the gate connections further comprise bump or ball connections on the gate pads.

13. The device of claim 12 further comprising a package, and wherein each of the plurality of source, drain and gate bump or ball connections are directly bonded to respective copper tracks of the package.

14. The device of claim 1 wherein the source island electrodes and drain island electrodes are substantially square shaped and said ball or bump connections are centred on each island.

15. A nitride semiconductor device comprising:

a) a conductive substrate;

b) a nitride semiconductor layer comprising a nitride semiconductor hetero-layer formed on a main surface of the substrate;

c) a plurality of source island electrodes and a plurality of drain island electrodes of a multi-island transistor formed on the nitride semiconductor layer, the source island electrodes and drain island electrodes being spaced apart from each other and arranged with alternating source island electrodes and drain island electrodes along at least two different axial directions to produce two-dimensional active regions in a device area of the nitride semiconductor layer, with;

i) at least one side of each of the source island electrodes opposite a side of an adjacent drain island electrode;

ii) at least one side of each of the drain island electrodes opposite a side of an adjacent source island electrode; and

d) a plurality of gate electrodes formed on the nitride semiconductor layer in active regions between each of the source island electrodes and each of the drain island electrodes, an overlying low resistance gate interconnect running between the source island electrodes and drain island electrodes, the plurality of gate electrodes being interconnected to the low resistance gate interconnect by interconnections at interstices defined by adjacent vertices of the source island electrodes and the drain island electrodes; and

e) each of the plurality of source island electrodes having a respective individual source contact area (pad) comprising a via connection to the conductive substrate;

f) each of the plurality of drain island electrodes having a respective individual drain contact area (pad) comprising a bump or ball connection formed thereon;

and

h) the low resistance gate interconnect being connected to a plurality of gate pads.

16. The device of claim 15 further comprising a copper thermal heat sink bonded to the backside of the conductive substrate in electrical contact therewith, and wherein the copper thermal heat sink provides a backside source connection.

17. The device of claim 16 further comprising a package and wherein the gate connections comprise bump or ball connections on the gate pads and wherein the drain bump or ball connections and the gate bump or ball connections are directly bonded to respective copper tracks of the package.

18. The device of claim 15 wherein the source island electrodes and drain island electrodes are substantially square shaped, and said ball or bump connections or via connections are centred on each island.