Electronic device including a tapered trench and a conductive structure therein

• US 9,064,949 B2
• Filed: 10/10/2013
• Issued: 06/23/2015
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Loechelt, Gary H.
• Primary Examiner(s): Diallo, Mamadou
• Assistant Examiner(s): SYLVIA, CHRISTINA A
• Application Number:
  US14/051,084
• Publication Number:
  US 20140035052A1
• Time in Patent Office: 621 Days
• Field of Search: 257/330, 257/288, 257/350, 257/E21.41, 257/E29.262, 257/77, 257/296, 257/301, 257/328, 257/324, 438/270, 438/430
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An electronic device can include a semiconductor layer, and a trench extending into the semiconductor layer and having a tapered shape. In an embodiment, the trench includes a wider portion and a narrower portion. The electronic device can include a doped semiconductor region that extends to a narrower portion of the trench and has a dopant concentration greater than a dopant concentration of the semiconductor layer. In another embodiment, the electronic device can include a conductive structure within a relatively narrower portion of the trench, and a conductive electrode within a relatively wider portion of the trench. In another embodiment, a process of forming the electronic device can include forming a sacrificial plug and may allow insulating layers of different thicknesses to be formed within the trench.

Claims

1. A transistor structure comprising:

a semiconductor layer overlying a substrate and having a primary surface that generally corresponds to a first plane;

a trench extending into the semiconductor layer and having a tapered shape including a relatively wider portion adjacent to the primary surface and a relatively narrower portion farther from the primary surface as compared to the relatively wider portion, wherein, from a cross-sectional view, the relatively narrower portion is defined by a substantially planar sidewall that lies along a second plane that intersects the first plane at an angle of greater than approximately 70°

;

a doped semiconductor region that lies adjacent to a sidewall of the trench having the tapered shape, wherein the doped semiconductor region extends to the narrower portion and has a dopant concentration greater than a dopant concentration of the semiconductor layer at a location adjacent to the primary surface, and wherein the doped semiconductor region is part of the drain region of the transistor structure; and

a gate member disposed outside of the trench.

2. The transistor structure of claim 1, further comprising a conductive structure disposed within the trench below the doped semiconductor region.

3. The transistor structure of claim 2, wherein the doped semiconductor region is electrically connected to the conductive structure.

4. The transistor structure of claim 3, further comprising an underlying doped region, wherein:

the semiconductor layer is disposed over the underlying doped region; and

the conductive structure is electrically connected to the underlying doped region.

5. The transistor structure of claim 1, wherein the transistor structure further comprises a gate disposed at an elevation above the primary surface.

6. The transistor structure of claim 1, wherein the doped semiconductor region has a dopant concentration in a range of approximately 5×

10¹⁶ atoms/cm³ to approximately 5×

10¹⁸ atoms/cm³.

7. The transistor structure of claim 1, wherein the tapered shape comprises a funnel shape.

8. A transistor structure comprising:

a semiconductor layer overlying a substrate and having a primary surface that generally corresponds to a first plane;

a trench having a first portion, a second portion, and a third portion, wherein;

the first, second, and third portions are disposed within the semiconductor layer;

the first and third portions are tapered; and

from a cross-sectional view, the second portion is defined by a sidewall that lies along a second plane that intersects the first plane at an angle of greater than approximately 70°

; and

a doped semiconductor region disposed along the first, second, and third portions of the trench;

wherein the doped semiconductor region is part of the drain region of the transistor structure.

9. The transistor structure of claim 8, wherein a dopant concentration of the doped semiconductor region is greater than a dopant concentration of the semiconductor layer at a location adjacent to the primary surface.

10. The transistor structure of claim 9, further comprising a conductive structure, wherein:

the trench has a fourth portion disposed within the semiconductor layer at an elevation below the first, second, and third portions of the trench; and

the conductive structure is disposed within the fourth portion of the trench.

11. The transistor structure of claim 10, wherein the fourth portion of the trench has a substantially vertical sidewall.

12. The transistor structure of claim 9, further comprising:

a first insulating layer disposed along the first portion of the trench;

a second insulating layer disposed along a second portion of the trench, wherein the second insulating layer is thicker than the first insulating layer; and

a conductive electrode, wherein;

the first insulating layer is disposed between the first portion of the trench and the conductive electrode; and

the second insulating layer is disposed between the second portion of the trench and the conductive electrode.

13. The transistor structure of claim 8, wherein the transistor structure further comprises a gate disposed at an elevation above the primary surface.

14. The transistor structure of claim 8, further comprising a conductive structure disposed within the trench and electrically connected to the doped semiconductor region.

15. An electronic device comprising:

a semiconductor layer overlying a substrate and having a primary surface, wherein the primary surface generally lies substantially along a plane;

a trench having a tapered shape;

a conductive structure within a relatively narrower portion of the trench;

a conductive electrode within a relatively wider portion of the trench, wherein the conductive electrode and the conductive structure are electrically insulated from each other; and

a doped semiconductor region adjacent to the primary surface and electrically connected to the conductive structure.

16. The electronic device of claim 15, wherein the conductive electrode extends into the trench such that a lowest elevation of the conductive electrode is at least approximately 0.3 microns below an elevation of the plane corresponding to the primary surface.

17. The electronic device of claim 15, further comprising:

a doped semiconductor region adjacent to the tapered portion, wherein a dopant concentration of the doped semiconductor region is greater than a dopant concentration of the semiconductor layer at a location adjacent to the primary surface; and

an insulating layer disposed between the doped semiconductor region and the conductive electrode, wherein;

the insulating layer has a first portion and a second portion; and

as compared to the second portion of the insulating layer, the first portion of the insulating layer is thinner and disposed closer to the primary surface.

18. The electronic device of claim 15, wherein the tapered shape comprises a funnel shape.

19. The electronic device of claim 15, wherein a first portion of the conductive electrode lies above the primary surface, and wherein a second portion of the conductive electrode extends into the trench.

20. The electronic device of claim 15, further comprising a gate member disposed outside of the trench.