Signal distribution networks and related methods

• US 9,065,453 B2
• Filed: 11/25/2013
• Issued: 06/23/2015
• Est. Priority Date: 10/15/2009
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Aryanfar, Farshid, Lee, Hae-Chang, Chang, Kun-Yung, Werner, Carl, Koochakzadeh, Masoud, Wu, Ting
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US14/089,094
• Publication Number:
  US 20140333356A1
• Time in Patent Office: 575 Days
• Field of Search: 327/149, 327/158
• US Class Current: 1/1
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.

Claims

1. A clock-distribution network comprising:

a first input node to receive a clock signal;

a buffer circuit connected to the first input node to receive and transmit the clock signal;

a first transmission line coupled to the buffer circuit to convey the transmitted clock signal to an intermediate node;

a second transmission line coupled to the first transmission line to convey the transmitted clock signal from the intermediate node to an first output node;

an inductor coupled between the intermediate node and a reference, the inductor exhibiting an inductance; and

a variable capacitance circuit coupled between the intermediate node and the reference, the variable capacitance circuit exhibiting a variable capacitance to determine a phase of the transmitted clock signal at the first output node.

2. The clock-distribution network of claim 1, further comprising a phase detector coupled between the first input node and the first output node, the phase detector to generate a control signal responsive to a phase offset between the clock signal at the first input node and the transmitted clock signal at the first output node.

3. The clock-distribution network of claim 2, the phase detector communicating with the variable capacitance circuit to vary the variable capacitance responsive to the control signal.

4. The clock-distribution network of claim 3, further comprising a filter disposed between the phase detector and the variable capacitance circuit, the filter to filter the control signal.

5. The clock-distribution network of claim 2, the phase detector communicating with the inductor to control the inductance responsive to the control signal.

6. The clock-distribution network of claim 1, further comprising:

a second input node to receive a second clock signal complementary to the clock signal, the buffer circuit connected to the second input node to receive and transmit the second clock signal;

a third transmission line coupled to the buffer circuit to convey the transmitted second clock signal to a second intermediate node, the second intermediate node serving as the reference; and

a fourth transmission line coupled to the third transmission line to convey the transmitted complementary second clock signal from the second intermediate node to a second output node.

7. The clock-distribution network of claim 6, further comprising a phase detector having a first phase-detector input coupled to the first input node and the second input node and a second phase-detector input coupled to the first output node and the second output node, the phase detector to generate a control signal responsive to a phase offset between the first phase-detector input and the second phase-detector input.

8. The clock-distribution network of claim 1, wherein the buffer circuit, the first transmission line, the second transmission line, the inductor, and the variable capacitance circuit constitute a segment, the clock-distribution network comprising multiple segments coupled in series.

9. The clock-distribution network of claim 8, wherein each of the segments includes an instance of the buffer circuit, the first transmission line, the second transmission line, the inductor, and the variable capacitance circuit.

10. The clock-distribution network of claim 9, further comprising a phase detector coupled between the first input node of a first of the segments in the series of segments and the first output node of a last of the segments in the series of segments.

11. The clock-distribution network of claim 10, the phase detector to generate a control signal responsive to a phase offset between the clock signal at the first input node of the first of the segments and the transmitted clock signal at the first output node of the last of the segments, the control signal to adjust the variable capacitance circuit in each of the segments.

12. The clock-distribution network of claim 1, further comprising an amplitude detector coupled between the first input node and the first output node, the amplitude detector to generate a control signal responsive to an amplitude of the transmitted clock signal at the first output node.

13. The clock-distribution network of claim 12, wherein the amplitude detector generates the control signal responsive to the amplitude of the transmitted clock signal at the first output node and an amplitude of the clock signal at the first input node.

14. The clock-distribution network of claim 13, further comprising adjusting a gain of the buffer circuit responsive to the control signal.

15. A clock-distribution network comprising:

an input node to receive a clock signal of a clock frequency;

a series of segments to convey the clock signal, each segment including;

a buffer circuit to amplify the clock signal;

a transmission line to convey the clock signal, amplified, from the buffer; and

a variable impedance coupled to the transmission line;

the transmission line and variable impedance exhibiting a resonant frequency greater than the clock frequency; and

a phase detector coupled to one of the buffer circuits and one of the transmission lines to detect a phase offset between instances of the clock signal along the clock-distribution network and to adjust at least one of the variable impedances responsive to the phase offset.

16. The network of claim 15, wherein the input nodes is one of two differential input nodes and the clock-distribution network is differential network.

17. The network of claim 15, wherein the phase detector sets the variable impedance so each segments exhibits a zero phase offset to the clock signal.

18. The network of claim 15, further comprising an amplitude detector coupled to one of the transmission lines to detect an amplitude of the clock signal, the network to adjust a gain of at least one of the buffers responsive to the amplitude of the clock signal.

19. The network of claim 15, wherein at least one of the segments comprises a delay-locked loop circuit.

20. The network claim 15, wherein the variable impedance includes an inductor.