Phase locked loop with self-calibration

• US 9,065,454 B2
• Filed: 02/22/2013
• Issued: 06/23/2015
• Est. Priority Date: 11/29/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yu-Tso
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): CHEN, PATRICK C
• Application Number:
  US13/774,757
• Publication Number:
  US 20140145769A1
• Time in Patent Office: 851 Days
• Field of Search: 327/156
• US Class Current: 1/1
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A method for self-calibrating a phase locked loop (PLL) includes setting a frequency range setting of a voltage controlled oscillator (VCO) to a first digital value for a first output frequency. A first difference is measured between a reference frequency and a feedback frequency resulting from the first output frequency. The frequency range setting is set to an inverted digital value of the first digital value for a second output frequency. A second difference is measured between the reference frequency and the feedback frequency resulting from the second output frequency. A value of the frequency range setting is selected based on the first difference and the second difference.

Claims

1. A method for self-calibrating a phase locked loop (PLL), comprising:

setting a frequency range setting of a voltage controlled oscillator (VCO) to a series of sequential digital values for a series of respective sequential output frequencies, including setting the frequency range to a first digital value for a first output frequency, wherein in an initial setting of the frequency range to a first digital value the first digital value is set to 2^(N-1), N being a number of bits of the frequency range setting, wherein N is at least three;

measuring a first difference between a reference frequency and a feedback frequency resulting from the first output frequency;

calculating an inverted digital value of the first digital;

setting the frequency range setting to the inverted digital value of the first digital value calculated in the calculating step as the next digital value in the series of sequential digital values for a second output frequency;

measuring a second difference between the reference frequency and the feedback frequency resulting from the second output frequency; and

selecting a value of the frequency range setting based at least in part on the first difference and the second difference.

2. The method of claim 1, further comprising deciding whether a target frequency is between the first output frequency and the second output frequency.

3. The method of claim 2, further comprising changing the first digital value of the frequency range setting if the target frequency is not between the first output frequency and the second output frequency.

4. The method of claim 1, further comprising setting a VCO input voltage to an initial voltage.

5. The method of claim 4, wherein the initial voltage is a middle voltage value of a range of the VCO input voltage.

6. The method of claim 4, wherein the initial voltage is provided by a controlled voltage circuit.

7. The method of claim 6, further comprising disconnecting from the controlled voltage circuit by a switch after selecting the value of the frequency range setting.

8. The method of claim 1, further comprising providing a reset signal to initialize the frequency range setting.

9. The method of claim 1, wherein measuring the first difference is based on a first time difference between rising edges of signals corresponding to the reference frequency and the feedback frequency.

10. The method of claim 1, wherein measuring the second difference is based on a second time difference between rising edges of signals corresponding to the reference frequency and the feedback frequency.

11. A phase locked loop (PLL) with self-calibration, comprising:

a voltage controlled oscillator (VCO); and

a controller module adapted to;

set a frequency range setting of the VCO to a series of sequential digital values for a series of respective sequential output frequencies, including a first digital value for a first output frequency, wherein in an initial value of the first digital value is 2^(N-1), N being a number of bits of the frequency range setting, wherein N is at least three;

measure a first difference between a reference frequency and a feedback frequency resulting from the first output frequency;

set the frequency range setting to an inverted digital value of the first digital value for a second output frequency as the next digital value in the series of sequential digital values;

measure a second difference between the reference frequency and the feedback frequency resulting from the second output frequency; and

select a value of the frequency range setting based on the first difference and the second difference.

12. The PLL of claim 11, wherein the controller module is further adapted to decide whether a target frequency is between the first output frequency and the second output frequency.

13. The PLL of claim 12, wherein the controller module is further adapted to change the first digital value of the frequency range setting if the target frequency is not between the first output frequency and the second output frequency.

14. The PLL of claim 11, wherein the controller module is further adapted to set a VCO input voltage to an initial voltage.

15. The PLL of claim 14, wherein the initial voltage is a middle voltage value of a range of the VCO input voltage.

16. The PLL of claim 14, wherein the initial voltage is provided by a controlled voltage circuit.

17. The PLL of claim 16, wherein the controller module is further adapted to disconnect from the controlled voltage circuit after selecting the value of the frequency range setting.

18. The PLL of claim 11, wherein the controller module is further adapted to provide a reset signal to initialize the frequency range setting.

19. An integrated circuit having a phase locked loop (PLL) comprising:

a voltage controlled oscillator (VCO) controller for setting a frequency range setting of a voltage controlled oscillator (VCO) to a series of sequential digital values for a series of respective sequential output frequencies, there being more than four output frequencies in the series of respective sequential output frequencies, including a first digital value for a first output frequency and setting the frequency range setting to an inverted digital value of the first digital value for a second output frequency as the next digital value in the series of sequential digital values, an initial value of the first output frequency being a middle output frequency in the series of respective sequential output frequencies; and

a PLL controller for measuring a first difference between a reference frequency and a feedback frequency resulting from the first output frequency, measuring a second difference between the reference frequency and the feedback frequency resulting from the second output frequency, and deciding whether a target frequency is between the first output frequency and the second output frequency;

wherein the VCO controller is configured to change the first digital value of the frequency range setting if the target frequency is not between the first output frequency and the second output frequency, and to select a value of the frequency range setting based on the first difference and the second difference.