Transmission system, transmission apparatus, and transmission method for transmitting video data

• US 9,065,963 B2
• Filed: 07/15/2014
• Issued: 06/23/2015
• Est. Priority Date: 05/16/2006
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Suzuki, Kazuyoshi, Matsuura, Katsuji
• Primary Examiner(s): Lee, Michael
• Application Number:
  US14/332,142
• Publication Number:
  US 20140354884A1
• Time in Patent Office: 343 Days
• Field of Search: 348553-558, 348469-478, 348/705, 348/706, 37524001-24029, 375/260, 375/259
• US Class Current: 1/1
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/12 Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
• CPC Class Codes: G09G 2370/047 using display data channel standard [DDC] communication
• CPC Class Codes: G09G 5/003 Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto specific for a CRT G09G1/165; for a flat panel G09G3/2092
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: H04N 5/04 Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 7/015 High-definition television systems
• CPC Class Codes: H04N 7/035 Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal
• CPC Class Codes: H04N 7/0803 using frequency interleaving, e.g. with precision offset
• CPC Class Codes: H04N 7/081 the additional information signals being transmitted by means of a subcarrier
• CPC Class Codes: H04N 7/083 with signal insertion during the vertical and the horizontal blanking interval , e.g. MAC data signals
• CPC Class Codes: H04N 7/087 with signal insertion during the vertical blanking interval only
• CPC Class Codes: H04N 7/088 the inserted signal being digital
• CPC Class Codes: H04N 7/10 Adaptations for transmission by electrical cable H04N7/12 takes precedence

Abstract

An HDMI® source determines whether or not an HDMI® sink can receive a sub-signal based on VSDB of E-EDID. When the HDMI® sink can receive the sub-signal, the HDMI® source adds a sub-signal to pixel data of a main image composed of pixel data whose number of bits is smaller than that of transmission pixel data transmitted by a transmitter, thereby constructing transmission pixel data. This data is transmitted by the transmitter through TMDS channels #0 to #2. Furthermore, the HDMI® source transmits a general control packet containing sub-signal information indicating whether or not the sub-signal is contained in the transmission pixel data in the control period of a vertical blanking period. The present invention can be applied to, for example, HDMI®.

Claims

1. A reception apparatus for receiving 24 bit pixel data of an uncompressed image for one screen transmitted in one direction from a transmitting apparatus using a differential signal transmitted via a plurality of transition minimized differential signaling (TMDS) channels, the TMDS channels being operable to transmit data of a fixed number of bits per clock transition of a pixel clock in a valid image period, the valid image period being a period between sequential vertical synchronization signals and not including a horizontal blanking period and a vertical blanking period, the reception apparatus comprising:

a transmitting unit that, via a display data channel (DDC) line, transmits high resolution image data related information which indicates whether or not the reception apparatus supports a high resolution image having pixel data of 30 bit, 36 bit or 48 bit, in which the high resolution image data related information is described in High Definition Multimedia Interface (HDMI) Vender Specific Definition Bit (VSDB) of Enhanced Extended Display Identification Data (E-EDID) stored in the reception apparatus;

a receiving unit that receives, from the transmission apparatus based on a determination whether or not the reception apparatus supports a high resolution image based on the high resolution image data related information, high resolution image data transmitted in one direction to the reception apparatus by using a differential signal transmitted via the plurality of TMDS channels in the valid image period, raising a frequency of the pixel clock, and inserting a color depth (CD) bit, which is related to a bit number of the high resolution image data, into a general control packet, the general control packet including a general control packet header and a general control subpacket including CD values, being transmitted during a data island period of the high resolution image data in one direction to the reception apparatus, in which the CD values of CD2=1, CD1=0 and CD0=1 indicate 30 bits per pixel, the CD values of CD2=1, CD1=1 and CD0=0 indicate 36 bits per pixel, and the CD values of CD2=1, CD1=1 and CD0=1 indicate 48 bits per pixel,

wherein, after the transmission apparatus raises the frequency of the pixel clock, one pixel data of the high resolution image data of 30 bit transmitted in 1.25 pixel clock transitions, one pixel data of the high resolution image data of 36 bit transmitted in 1.5 pixel clock transitions, or one pixel data of the high resolution image data of 48 bit transmitted in two pixel clock transitions is received by the reception apparatus.

2. A reception method for receiving 24 bit pixel data of an uncompressed image for one screen transmitted in one direction from a transmitting apparatus to a receiving apparatus by using a differential signal transmitted via a plurality of transition minimized differential signaling (TMDS) channels, the TMDS channels being operable to transmit data of a fixed number of bits per clock transition of a pixel clock in a valid image period, the valid image period being a period between sequential vertical synchronization signals and not including a horizontal blanking period and a vertical blanking period, the reception method comprising:

transmitting, via a display data channel (DDC) line, high resolution image data related information which indicates whether or not the receiving apparatus supports a high resolution image having pixel data of 30 bit, 36 bit or 48 bit, in which the high resolution image data related information is described in High Definition Multimedia Interface (HDMI) Vender Specific Definition Bit (VSDB) of Enhanced Extended Display Identification Data (E-EDID) stored in the receiving apparatus;

receiving, from the transmission apparatus based on a determination whether or not the receiving apparatus supports a high resolution image based on the high resolution image data related information, high resolution image data transmitted in one direction to the receiving apparatus by using a differential signal transmitted via the plurality of TMDS channels in the valid image period, raising a frequency of the pixel clock, and inserting a color depth (CD) bit, which is related to a bit number of the high resolution image data, into a general control packet, the general control packet including a general control packet header and a general control subpacket including CD values, being transmitted during a data island period of the high resolution image data in one direction to the receiving apparatus, in which the CD values of CD2=1, CD1=0 and CD0=1 indicate 30 bits per pixel, the CD values of CD2=1, CD1=1 and CD0=0 indicate 36 bits per pixel, and the CD values of CD2=1, CD1=1 and CD0=1 indicate 48 bits per pixel,

wherein, after the transmission apparatus raises the frequency of the pixel clock, one pixel data of the high resolution image data of 30 bit transmitted in 1.25 pixel clock transitions, one pixel data of the high resolution image data of 36 bit transmitted in 1.5 pixel clock transitions, or one pixel data of the high resolution image data of 48 bit transmitted in two pixel clock transitions is received.