Microfabricated ultrasonic transducers and related apparatus and methods

• US 9,067,779 B1
• Filed: 03/02/2015
• Issued: 06/30/2015
• Est. Priority Date: 07/14/2014
• Status: Active Grant

• Current Assignee: BFLY Operations, Inc. (Butterfly Network, Inc.)
• Original Assignee: Butterfly Network, Inc.
• Inventors: Rothberg, Jonathan M., Alie, Susan A., Fife, Keith G., Sanchez, Nevada J., Ralston, Tyler S.
• Primary Examiner(s): Kim, Su C
• Application Number:
  US14/635,197
• Time in Patent Office: 120 Days
• US Class Current: 1/1
• CPC Class Codes: A61B 8/4483 characterised by features of the ultrasound transducer
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: B81C 2203/036 Fusion bonding
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: G01N 29/2406 Electrostatic or capacitive probes, e.g. electret or cMUT-probes
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/146 Mixed devices
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

Claims

1. A method, comprising:

forming a layer of silicon oxide on a first side of a first wafer, the first wafer having a second side opposite the first side;

forming a plurality of cavities in the layer of silicon oxide;

bonding a second wafer with the first wafer such that the second wafer seals the plurality of cavities in the layer of silicon oxide;

annealing the first wafer and the second wafer after bonding them together, the annealing utilizing a temperature above 500°

C.;

thinning the first wafer or the second wafer after the annealing to create a thinned wafer with a thickness less than 30 microns and greater than 4 microns;

etching a plurality of trenches in the thinned wafer, the plurality of trenches defining a plurality of electrode regions of the thinned wafer;

filling the plurality of trenches with an insulating material;

forming metal contacts on the thinned wafer, at least some of the metal contacts corresponding to the plurality of electrode regions;

bonding the thinned wafer with a complementary metal oxide semiconductor (CMOS) wafer having integrated circuitry formed therein using the metal contacts on the thinned wafer to contact bonding points on the CMOS wafer, wherein bonding the thinned wafer with the CMOS wafer is performed below 450°

C.; and

thinning, after bonding the thinned wafer with the CMOS wafer, the first wafer or the second wafer, whichever was not previously thinned as part of forming the thinned wafer.

2. The method of claim 1, wherein the first wafer is a bulk silicon wafer, and wherein thinning the first wafer or the second wafer after the annealing to create a thinned wafer comprises thinning the first wafer from the second side of the first wafer.

3. The method of claim 2, wherein thinning the first wafer from the second side of the first wafer comprises using a timed etch.

4. The method of claim 2, wherein the first wafer comprises a doped silicon layer proximate the first side, and wherein thinning the first wafer from the second side of the first wafer comprises thinning the first wafer to the doped silicon layer.

5. The method of claim 2, wherein the second wafer is a silicon-on-insulator (SOI) wafer, and wherein thinning, after bonding the thinned wafer with the CMOS wafer, the first wafer or the second wafer, whichever was not previously thinned as part of forming the thinned wafer, comprises thinning the SOI wafer by removing a handle layer of the SOI wafer.

6. The method of claim 1, wherein the second wafer is a bulk silicon wafer, and wherein thinning the first wafer or the second wafer after the annealing to create a thinned wafer comprises thinning the second wafer.

7. The method of claim 6, wherein the first wafer is a silicon-on-insulator (SOI) wafer, and wherein thinning, after bonding the thinned wafer with the CMOS wafer, the first wafer or the second wafer, whichever was not previously thinned as part of forming the thinned wafer, comprises thinning the SOI wafer by removing a handle layer of the SOI wafer.

8. The method of claim 1, wherein the first wafer is a silicon-on-insulator (SOI) wafer, and wherein thinning the first wafer or the second wafer after the annealing to create a thinned wafer comprises thinning the SOI wafer by removing a handle layer of the SOI wafer.

9. The method of claim 8, wherein the second wafer is a SOI wafer, and wherein thinning, after bonding the thinned wafer with the CMOS wafer, the first wafer or the second wafer, whichever was not previously thinned as part of forming the thinned wafer, comprises thinning the second wafer by removing a handle layer of the second wafer.

10. The method of claim 1, wherein the method does not involve forming a thru-silicon via (TSV).

11. The method of claim 1, wherein the first wafer or the second wafer, whichever is thinned to create the thinned wafer, comprises at least one thru-silicon via (TSV).

12. The method of claim 1, further comprising, prior to bonding the thinned wafer with the CMOS wafer, etching a clear out region through the thinned wafer.

13. The method of claim 1, wherein the method does not involve the use of chemical mechanical polishing (CMP).

14. The method of claim 1, wherein annealing the first wafer and the second wafer utilizes a temperature less than 1,500°

C.

15. The method of claim 1, further comprising forming an embedded via in the first wafer or the second wafer, whichever is thinned to create the thinned wafer.

16. The method of claim 15, wherein the embedded via provides electrical connection between the integrated circuitry and the first wafer or the second wafer, whichever was not thinned as part of forming the thinned wafer.