System and method for monitoring two-wire communication in a network environment

• US 9,069,483 B2
• Filed: 07/21/2014
• Issued: 06/30/2015
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Bamford, Harold E., Mila, Ted R.
• Primary Examiner(s): STIGLIC, RYAN M
• Application Number:
  US14/336,511
• Publication Number:
  US 20140330997A1
• Time in Patent Office: 344 Days
• Field of Search: 710/110, 710/200, 710/313, 710/314
• US Class Current: 1/1
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 13/4004 Coupling between buses
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Abstract

An example method is provided and includes receiving, from a host device, a first signal over a two-wire bus to an address on the two-wire bus corresponding to a small form factor (XFP) module, the host device being located outside the XFP module, the two-wire bus coupling the host device with a first controller inside the XFP module and a second controller inside the XFP module that share the address such that the first controller and the second controller receive the first signal, and blocking a second signal from the second controller to the host device using digital isolation buffers. A third signal from the first controller to the host device over the two-wire bus is not blocked. In specific embodiments, the first controller includes a XFP compliant controller and the second controller includes an optical controller.

Claims

1. A method, comprising:

receiving, from a host device, a first signal transmitted over a two-wire bus to an address on the two-wire bus corresponding to a small form factor (XFP) module, the host device being located outside the XFP module, the two-wire bus coupling the host device with a first controller inside the XFP module and a second controller inside the XFP module that share the address such that the first controller and the second controller receive the first signal; and

blocking a second signal from the second controller to the host device using digital isolation buffers.

2. The method of claim 1, wherein a third signal from the first controller to the host device over the two-wire bus is not blocked.

3. The method of claim 1, wherein the first controller comprises a XFP compliant controller and the second controller comprises an optical controller.

4. The method of claim 1, wherein outputs of the digital isolation buffers are sent to the second controller.

5. The method of claim 1, wherein the second controller responds to the first signal with the second signal.

6. The method of claim 1, wherein the first signal comprises a write operation of calibration values to the first controller'"'"'s memory, wherein the second controller allows the calibration values to be written to the second controller'"'"'s memory if the calibration values are of interest to the second controller.

7. The method of claim 6, wherein the second controller uses the written values as calibration values for appropriate parameters.

8. The method of claim 1, wherein the first signal comprises a read operation of a particular memory address in the XFP module, wherein the digital isolation buffers block any response by the second controller to the read operation.

9. The method of claim 1, wherein an internal bootstrap loader allows the second controller to be programmed over the two-wire bus.

10. The method of claim 1, wherein the first controller serves as a proxy for the second controller, wherein the second controller cannot communicate with the host device such that it can send signals over the two-wire bus, or fail to respond, without interfering with communication over the two-wire bus between the host device and the first controller.

11. Logic encoded in non-transitory media that includes code for execution and when executed by a processor is operable to perform operations comprising:

receiving, from a host device, a first signal transmitted over a two-wire bus to an address on the two-wire bus corresponding to an XFP module, the host device being located outside the XFP module, the two-wire bus coupling the host device with a first controller inside the XFP module and a second controller inside the XFP module that share the address such that the first controller and the second controller receive the first signal; and

blocking a second signal from the second controller to the host device using digital isolation buffers.

12. The logic of claim 11, wherein a third signal from the first controller to the host device over the two-wire bus is not blocked.

13. The logic of claim 11, wherein the first controller comprises a XFP compliant controller and the second controller comprises an optical controller.

14. The logic of claim 11, wherein the first signal comprises a write operation of calibration values to the first controller'"'"'s memory, wherein the second controller allows the calibration values to be written to the second controller'"'"'s memory if the calibration values are of interest to the second controller.

15. The logic of claim 11, wherein the first signal comprises a read operation of a particular memory address in the XFP module, wherein the digital isolation buffers block any response by the second controller to the read operation.

16. An apparatus having an address on a two-wire bus, comprising:

a memory configured to store data;

a processor operable to execute instructions associated with the data;

a first controller and a second controller connected on the two-wire bus at the address;

digital isolation buffers such that the apparatus is configured for;

receiving a first signal transmitted from a host device located outside the apparatus to the address over the two-wire bus, such that the first controller and the second controller receive the first signal; and

blocking a second signal from the second controller to the host device using the digital isolation buffers.

17. The apparatus of claim 16, wherein a third signal from the first controller to the host device over the two-wire bus is not blocked.

18. The apparatus of claim 16, wherein the first controller comprises a XFP compliant controller and the second controller comprises an optical controller.

19. The apparatus of claim 16, wherein the first signal comprises a write operation of calibration values to the first controller'"'"'s memory, wherein the second controller allows the calibration values to be written to the second controller'"'"'s memory if the calibration values are of interest to the second controller.

20. The apparatus of claim 16, wherein the first signal comprises a read operation of a particular memory address in the XFP module, wherein the digital isolation buffers block any response by the second controller to the read operation.