Electronic devices having integrated reset systems and methods thereof

• US 9,069,536 B2
• Filed: 10/30/2012
• Issued: 06/30/2015
• Est. Priority Date: 10/31/2011
• Status: Active Grant

• Current Assignee: Abbott Diabetes Care Incorporated (Abbott Laboratories Incorporated)
• Original Assignee: Abbott Diabetes Care Incorporated (Abbott Laboratories Incorporated)
• Inventors: Ghesquiere, Alexander G., Myles, Christopher Ammon, Dalton, Scott
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): ERDMAN, CHAD G
• Application Number:
  US13/664,061
• Publication Number:
  US 20130111248A1
• Time in Patent Office: 973 Days
• Field of Search: 439/522, 713/324, 713/330, 713/340
• US Class Current: 1/1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/3212 Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system

Abstract

Methods and devices for power cycling an electronic device are provided. Also provided are systems and kits.

Claims

1. A method of power cycling an electronic device having a data processor, the method comprising:

enabling a reset circuit to provide a reset signal to a data processor of an electronic device to initiate a first power reset cycle;

supplying power to the data processor while enabling the reset circuit to initialize the electronic device to a known state;

disabling the reset circuit while maintaining power to the data processor to operate the electronic device and to complete the first power reset cycle;

enabling the reset circuit while maintaining power to the data processor to initiate a second power reset cycle;

removing power to the data processor while the reset circuit is enabled to perform the second power reset cycle; and

disabling the reset circuit to complete the second power reset cycle.

2. The method of claim 1, wherein the enabling the reset circuit comprises conductively grounding the reset circuit.

3. The method of claim 2, wherein the conductively grounding the reset circuit comprises positioning one pole of a battery across two reset contact points.

4. The method of claim 3, wherein the supplying power to the data processor comprises positioning the battery between ground and a power circuit of the device.

5. The method of claim 4, wherein the disabling the reset circuit includes removing the battery from the two reset contact points.

6. An electronic device including a device housing that encases power cycling electronic components of the electronic device, comprising:

a printed circuit board including a data processor;

a power interface circuit that provides at least one power input line to the data processor;

a reset circuit that provides a reset signal to the data processor via a reset line, the reset circuit including a reset switch comprising at least one reset pad provided on the printed circuit board, the reset circuit configured to initiate a power reset cycle of the electronic device;

a battery receptacle configured to receive a battery pack including at least one cathode terminal and at least one anode terminal; and

the battery pack including a housing and at least one battery retained in the housing and positioned between the at least one cathode terminal and the at least one anode terminal, the battery configured to provide power to the electronic device, wherein the insertion of the battery pack into the battery receptacle triggers the reset circuit to initiate the power reset cycle of the electronic device, to initialize the electronic device to a known state, and to complete the initiated power reset cycle.

7. The electronic device of claim 6, wherein the data processor includes a microprocessor.

8. The electronic device of claim 6, wherein a separation distance between the at least one cathode terminal and the at least one anode terminal is less than a thickness of the at least one battery.

9. The electronic device of claim 6, wherein the at least one anode terminal is anchored with a spring bias that enables a bending of the at least one anode terminal upon receipt of the at least one battery between the at least one cathode terminal and the at least one anode terminal.

10. The electronic device of claim 6, wherein the at least one reset pad includes a first reset pad electrically coupled to device ground and a second reset pad electrically coupled to an input of the reset circuit.

11. The electronic device of claim 6, wherein a height of the at least one reset pad is greater than a top surface of the at least one cathode terminal.

12. The electronic device of claim 11, wherein the height of the at least one reset pad is in a range of 0.01 mm to 1.0 mm.

13. The electronic device of claim 6, wherein the at least one battery is a replaceable battery.

14. The electronic device of claim 6, wherein the battery pack is configured to engage with the battery receptacle in a sliding or snap-fit manner.

15. The electronic device of claim 6, wherein the at least one reset pad is laterally spaced from a leading peripheral edge of the at least one cathode terminal.

16. The electronic device of claim 15, wherein the lateral spacing of the at least one reset pad from the leading peripheral edge of the at least one cathode terminal is in a range of 0.01 mm to 10 mm.

17. A method of power cycling an electronic device having a data processor, the method comprising:

receiving, at one or more reset contact points, an electrical short from at least one battery by positioning one pole of the battery over the one or more reset contact points;

receiving, at one or more data processors, a first voltage input signal from one or more reset lines that is HI to initiate a power reset cycle of an electronic device;

receiving, at the one or more data processors, a second voltage input signal from one or more power lines that is LO;

receiving, at the one or more data processors, a third voltage input signal from the one or more power lines that is HI to initialize the electronic device to a known state;

determining, at the one or more data processors, that the first voltage input signal from the one or more reset lines remains HI;

receiving, at the one or more data processors, a fourth voltage input signal from the one or more reset lines that is LO to complete the power reset cycle; and

determining, at the one or more data processors, that the third voltage input signal from the one or more power lines remains HI to operate the electronic device.