Integrated level shifting latch circuit and method of operation of such a latch circuit

• US 9,069,652 B2
• Filed: 03/01/2013
• Issued: 06/30/2015
• Est. Priority Date: 03/01/2013
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Yeung, Gus, Guo, Frank, Zheng, Bo
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US13/782,077
• Publication Number:
  US 20140250278A1
• Time in Patent Office: 851 Days
• Field of Search: 365/189.11, 365/189.08, 365/189.16, 365/189.12, 365/205, 365/228, 327/74, 327/333, 326/63, 326/68, 326/80, 326/81
• US Class Current: 1/1
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches

Abstract

An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal. Control circuitry controls the data retention circuitry to operate in the transparent phase during a first phase of the clock signal and to operate in the latching phase during a second phase of the clock signal. Writing circuitry writes the data value into the data retention circuitry. Contention mitigation circuitry, during the transparent phase, reduces a voltage drop across at least one component within the data retention circuitry.

Claims

1. An integrated level shifting latch circuit for receiving an input signal in a first voltage domain and generating an output signal in a second voltage domain, said first voltage domain operating with a first voltage supply providing a first voltage level and a common voltage level and said second voltage domain operating with a second voltage supply providing a second voltage level and said common voltage level, said integrated level shifting latch circuit comprising:

data retention circuitry operating in said second voltage domain and configured to operate in a transparent phase where a data value is subjected to a level shifting function and written into the data retention circuitry dependent on the input signal, and a latching phase where the data value written into the data retention circuitry during the transparent phase is retained irrespective of any change in the input signal during the latching phase, and that retained data value forms said output signal;

control circuitry configured to receive a clock signal and to control the data retention circuitry to operate in said transparent phase during a first phase of the clock signal and to operate in said latching phase during a second phase of the clock signal;

writing circuitry configured during the transparent phase to write said data value into said data retention circuitry by controlling a voltage of at least one internal node of the data retention circuitry dependent on the input signal; and

contention mitigation circuitry configured to receive said input signal and, during said transparent phase, to reduce a voltage drop across at least one component within the data retention circuitry, thereby assisting said writing circuitry in altering the voltage of said at least one internal node during the transparent phase.

2. An integrated level shifting latch circuit as claimed in claim 1, wherein a difference between said second voltage level and said common voltage level is higher than a difference between said first voltage level and said common voltage level.

3. An integrated level shifting latch circuit as claimed in claim 2, wherein said contention mitigation circuitry operates in said second voltage domain and, based on the input signal in said first voltage domain, presents a resistive path during said transparent phase which prevents a short circuit path occurring through the integrated level shifting latch circuit in the transparent phase.

4. An integrated level shifting latch circuit as claimed in claim 1, wherein said level shifting function is performed via an arrangement of components within the data retention circuitry that provides a feedback mechanism.

5. An integrated level shifting latch circuit as claimed in claim 1, wherein:

said contention mitigation circuitry is connected between a first node and a second node;

a first portion of said control circuitry is connected in parallel with said contention mitigation circuitry between said first node and said second node, in the latching phase said first portion of said control circuitry connecting the first and second nodes to thereby prevent operation of the contention mitigation circuitry during said latching phase.

6. An integrated level shifting latch circuit as claimed in claim 5, wherein said second node comprises a first second node portion and a second second node portion, in at least said transparent phase the first second node portion and the second second node portion being disconnected from each other to allow the voltage level at the first second node portion to differ from the voltage level at the second second node portion.

7. An integrated level shifting latch circuit as claimed in claim 6, wherein said first portion of said control circuitry is configured during said latching phase to connect the first second node portion and the second second node portion.

8. An integrated level shifting latch circuit as claimed in claim 6, wherein said contention mitigation circuitry comprises first PMOS transistor circuitry connected between said first node and said first second node portion, and second PMOS transistor circuitry connected between said first node and said second second node portion.

9. An integrated level shifting latch circuit as claimed in claim 1, wherein said contention mitigation circuitry is connected between said second voltage level and a first end of said data retention circuitry.

10. An integrated level shifting latch circuit as claimed in claim 1, wherein said contention mitigation circuitry is connected between internal nodes of the data retention circuitry.

11. An integrated level shifting latch circuit as claimed in claim 10, wherein said data retention circuitry comprises a cross-coupled pair of inverters formed from PMOS transistors and NMOS transistors, and the contention mitigation circuitry is connected between the PMOS transistors and the NMOS transistors of said cross-coupled pair of inverters.

12. An integrated level shifting latch circuit as claimed in claim 1, wherein;

said data retention circuitry comprises a cross-coupled pair of inverters formed from PMOS transistors and NMOS transistors; and

said control circuitry is configured during said transparent phase to disable the NMOS transistors of said cross-coupled pair of inverters.

13. An integrated level shifting latch circuit as claimed in claim 1, wherein said first phase of the clock signal is a logic 0 level, and said second phase of the clock signal is a logic 1 level.

14. An integrated level shifting latch circuit as claimed in claim 1, wherein said first phase of the clock signal is a logic 1 level, and said second phase of the clock signal is a logic 0 level.

15. An integrated level shifting latch circuit as claimed in claim 1, wherein said clock signal is generated in said first voltage domain.

16. An integrated level shifting latch circuit as claimed in claim 1, wherein said clock signal is generated in said second voltage domain.

17. An integrated level shifting latch circuit as claimed in claim 1, wherein said data retention circuitry comprises a cross-coupled pair of inverters formed from PMOS transistors and NMOS transistors, and said at least one component which has its voltage drop reduced by the contention mitigation circuitry during said transparent phase is at least one of said PMOS transistors.

20. A non-transitory, computer-readable program storage medium storing a memory compiler computer program for controlling a computer to generate an instance of a memory device from a memory architecture associated with the memory compiler computer program, the memory architecture specifying a definition of circuit elements and data defining rules for combining those circuit elements, such that said instance generated specifies a memory device incorporating an integrated level shifting latch circuit as claimed in claim 1.

18. A method of operating an integrated level shifting latch circuit configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, said first voltage domain operating with a first voltage supply providing a first voltage level and a common voltage level and said second voltage domain operating with a second voltage supply providing a second voltage level and said common voltage level, said method comprising:

employing data retention circuitry operating in said second voltage domain to operate in a transparent phase where a data value is subjected to a level shifting function and written into the data retention circuitry dependent on the input signal, and a latching phase where the data value written into the data retention circuitry during the transparent phase is retained irrespective of any change in the input signal during the latching phase;

outputting said retained data value as said output signal;

controlling the data retention circuitry in dependence on a received clock signal to operate in said transparent phase during a first phase of the clock signal and to operate in said latching phase during a second phase of the clock signal;

writing, during the transparent phase, said data value into said data retention circuitry by controlling a voltage of at least one internal node of the data retention circuitry dependent on the input signal; and

employing contention mitigation circuitry, during said transparent phase, to reduce a voltage drop across at least one component within the data retention circuitry based on said input signal, thereby assisting said writing step in altering the voltage of said at least one internal node during the transparent phase.

19. An integrated level shifting latch circuit for receiving an input signal in a first voltage domain and generating an output signal in a second voltage domain, said first voltage domain operating with a first voltage supply providing a first voltage level and a common voltage level and said second voltage domain operating with a second voltage supply providing a second voltage level and said common voltage level, said integrated level shifting latch circuit comprising:

data retention means for operating in said second voltage domain and for operating in a transparent phase where a data value is subjected to a level shifting function and written into the data retention means dependent on the input signal, and a latching phase where the data value written into the data retention means during the transparent phase is retained irrespective of any change in the input signal during the latching phase, and that retained data value forms said output signal;

control means for receiving a clock signal and for controlling the data retention means to operate in said transparent phase during a first phase of the clock signal and to operate in said latching phase during a second phase of the clock signal;

writing means for writing, during the transparent phase, said data value into said data retention means by controlling a voltage of at least one internal node of the data retention means dependent on the input signal; and

contention mitigation means for receiving said input signal and, during said transparent phase, for reducing a voltage drop across at least one component within the data retention means, thereby assisting said writing means in altering the voltage of said at least one internal node during the transparent phase.